root / Version 1.3 / RS232_MUX.X / hardware_TL16C754C.h @ f4f84cf1
Historique | Voir | Annoter | Télécharger (18,98 ko)
1 |
/* Microchip Technology Inc. and its subsidiaries. You may use this software
|
---|---|
2 |
* and any derivatives exclusively with Microchip products.
|
3 |
*
|
4 |
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER
|
5 |
* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED
|
6 |
* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A
|
7 |
* PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP PRODUCTS, COMBINATION
|
8 |
* WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
|
9 |
*
|
10 |
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
11 |
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
12 |
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
13 |
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE
|
14 |
* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS
|
15 |
* IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF
|
16 |
* ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
17 |
*
|
18 |
* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE OF THESE
|
19 |
* TERMS.
|
20 |
*/
|
21 |
|
22 |
/*
|
23 |
* File: hardware_TL16C754C.h
|
24 |
* Author: Enzo Niro
|
25 |
* Comments: Library for MUX232 to handle TL16C754C chip
|
26 |
* Revision history: 1.0
|
27 |
*/
|
28 |
|
29 |
|
30 |
#ifndef RS232_HARDWARETL16_H
|
31 |
#define RS232_HARDWARETL16_H
|
32 |
|
33 |
#include <xc.h> // include processor files - each processor file is guarded. |
34 |
|
35 |
|
36 |
|
37 |
|
38 |
//////////////////////////////////////
|
39 |
//prototypes functions
|
40 |
|
41 |
|
42 |
//////////////////////////
|
43 |
//High level functions
|
44 |
|
45 |
void initPortA(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit);
|
46 |
void initPortB(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit);
|
47 |
void initPortC(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit);
|
48 |
void initPortD(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit);
|
49 |
|
50 |
//Send bytes throught serial port
|
51 |
void txWriteA(uint8_t b);
|
52 |
void txWriteB(uint8_t b);
|
53 |
void txWriteC(uint8_t b);
|
54 |
void txWriteD(uint8_t b);
|
55 |
|
56 |
//Receive bytes from serial port
|
57 |
uint8_t rxReadA(void);
|
58 |
uint8_t rxReadB(void);
|
59 |
uint8_t rxReadC(void);
|
60 |
uint8_t rxReadD(void);
|
61 |
|
62 |
//RX buffer control
|
63 |
|
64 |
//available functions
|
65 |
bool portA_available();
|
66 |
bool portB_available();
|
67 |
bool portC_available();
|
68 |
bool portD_available();
|
69 |
|
70 |
//parity functions
|
71 |
|
72 |
/*
|
73 |
|
74 |
TODO : Implement functions...
|
75 |
|
76 |
*/
|
77 |
|
78 |
|
79 |
//////////////////////////
|
80 |
//Low level functions
|
81 |
|
82 |
|
83 |
void writePortA(uint8_t reg, uint8_t addr);
|
84 |
void writePortB(uint8_t reg, uint8_t addr);
|
85 |
void writePortC(uint8_t reg, uint8_t addr);
|
86 |
void writePortD(uint8_t reg, uint8_t addr);
|
87 |
uint8_t readPortA(uint8_t addr); |
88 |
uint8_t readPortB(uint8_t addr); |
89 |
uint8_t readPortC(uint8_t addr); |
90 |
uint8_t readPortD(uint8_t addr); |
91 |
|
92 |
|
93 |
void setWait(uint16_t cnt); //fast delay |
94 |
|
95 |
|
96 |
//////////////////////////////////////////////////////////
|
97 |
//Values definitions (not supposed to use it directly)
|
98 |
|
99 |
#define DLAB_ERF_EN_BIT 0x80 |
100 |
|
101 |
|
102 |
#define LCR_REG 0x3 //Static register |
103 |
|
104 |
///////////////////////////////////////////
|
105 |
// READ Registers
|
106 |
|
107 |
#define RHR_REG 0x0 |
108 |
#define IIR_REG 0x2 |
109 |
#define LSR_REG 0x5 |
110 |
#define MSR_REG 0x6 |
111 |
#define FIFORDY_REG 0x7 |
112 |
|
113 |
///////////////////////////////////////////
|
114 |
// WRITE Registers
|
115 |
|
116 |
#define THR_REG 0x0 |
117 |
#define FCR_REG 0x2 |
118 |
|
119 |
///////////////////////////////////////////
|
120 |
// READ/WRITE Registers
|
121 |
|
122 |
#define IER_REG 0x1 |
123 |
#define LCR_REG 0x3 |
124 |
#define MCR_REG 0x4 |
125 |
#define SPR_REG 0x7 |
126 |
#define DLL_REG 0x0 |
127 |
#define DLH_REG 0x1 |
128 |
#define EFR_REG 0x2 |
129 |
#define XON1_REG 0x4 |
130 |
#define XON2_REG 0x5 |
131 |
#define XOFF1_REG 0x6 |
132 |
#define XOFF2_REG 0x7 |
133 |
#define TCR_REG 0x6 |
134 |
#define TLR_REG 0x7 |
135 |
|
136 |
|
137 |
|
138 |
|
139 |
///////////////////////////////////////////////////////
|
140 |
//CTRL, ADDR and DATA buses
|
141 |
|
142 |
//Data pins
|
143 |
#define DATAWRITE(x) PORTD.OUT = x
|
144 |
#define DATADIR(x) PORTD.DIR = x
|
145 |
#define DATAREAD PORTD.IN
|
146 |
|
147 |
//Address pins
|
148 |
#define ADDRWRITE(x) PORTE.OUT = x
|
149 |
#define ADDR_ENABLE PORTE.DIR |= 0x07 |
150 |
|
151 |
|
152 |
//Controls pins
|
153 |
#define ENABLE_POW_SUPPLY_PIN PORTF.DIR |= 0x01 |
154 |
#define ENABLE_WR_RD_PINS PORTB.DIR |= 0x30 |
155 |
#define ENABLE_CS_PINS PORTB.DIR |= 0x0F |
156 |
#define ENABLE_RESET_PIN PORTE.DIR |= 0x08 |
157 |
#define POWER_ON PORTF.OUT |= 0x01 |
158 |
#define POWER_OFF PORTF.OUT &= ~(0x01) |
159 |
#define SETRST PORTE.OUT |= 0x08 |
160 |
#define SETWR PORTB.OUT |= 0x10 |
161 |
#define SETRD PORTB.OUT |= 0x20 |
162 |
#define SETCSA PORTB.OUT |= 0x01 |
163 |
#define SETCSB PORTB.OUT |= 0x02 |
164 |
#define SETCSC PORTB.OUT |= 0x04 |
165 |
#define SETCSD PORTB.OUT |= 0x08 |
166 |
#define CLRRST PORTE.OUT &= ~(0x08) |
167 |
#define CLRWR PORTB.OUT &= ~(0x10) |
168 |
#define CLRRD PORTB.OUT &= ~(0x20) |
169 |
#define CLRCSA PORTB.OUT &= ~(0x01) |
170 |
#define CLRCSB PORTB.OUT &= ~(0x02) |
171 |
#define CLRCSC PORTB.OUT &= ~(0x04) |
172 |
#define CLRCSD PORTB.OUT &= ~(0x08) |
173 |
|
174 |
///////////////////////////////////////////////////////////////////////////////
|
175 |
//Functions
|
176 |
|
177 |
//////////////////////////////////////
|
178 |
//High level functions
|
179 |
|
180 |
void initPortA(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit)
|
181 |
{ |
182 |
|
183 |
uint8_t regVal = 0; //temp value for reading register and change it's value without clearing it |
184 |
//void (*callFuncWR)();
|
185 |
//uint8_t (*callFuncRD)();
|
186 |
//uint16_t addrWriteFunc[] = {&writePortA, &writePortB, &writePortC, &writePortD};
|
187 |
//uint16_t addrReadFunc[] = {&readPortA, &readPortB, &readPortC, &readPortD};
|
188 |
//uint8_t wordValues[] = {TL16C_WORD_5BITS, TL16C_WORD_6BITS, TL16C_WORD_7BITS, TL16C_WORD_8BITS};
|
189 |
//uint8_t baudsValues[] = {DL_9600_BAUDS, DL_19200_BAUDS, DL_38400_BAUDS};
|
190 |
//uint8_t parityValues[] = {TL16C_PARITY_NONE, TL16C_PARITY_ODD, TL16C_PARITY_EVEN};
|
191 |
//uint8_t stopBitValues[] = {TL16C_STOPBIT_ONE, TL16C_STOPBIT_TWO};
|
192 |
|
193 |
//callFuncWR = uart_type > 3 ? writePortD : addrWriteFunc[uart_type];
|
194 |
//callFuncRD = uart_type > 3 ? writePortD : addrReadFunc[uart_type];
|
195 |
|
196 |
|
197 |
//Read register first...
|
198 |
regVal = readPortA(LCR_REG); |
199 |
//_delay_ms(1);
|
200 |
setWait(20);
|
201 |
regVal = DLAB_ERF_EN_BIT; //set LCR[7] = 1 -> enable divisor latch mode
|
202 |
writePortA(regVal, LCR_REG); //switch Mode
|
203 |
//_delay_ms(1);
|
204 |
setWait(20);
|
205 |
//Set bus speed (according of 8MHz OSC. -> DL = Fosc/(16*Fbauds*DIV));
|
206 |
//DIV = 1 or 4 (see TL16C datasheet p.14), we use here DIV = 1
|
207 |
writePortA(0x00, DLH_REG); //Always 0x00 in our cfg... MAX 12MHz |
208 |
//_delay_ms(1);
|
209 |
setWait(20);
|
210 |
//writePortA(busSpeed > 2 ? DL_38400_BAUDS : baudsValues[busSpeed], DLL_REG);
|
211 |
writePortA(busSpeed, DLL_REG); |
212 |
//_delay_ms(1);
|
213 |
setWait(20);
|
214 |
|
215 |
regVal = readPortA(LCR_REG); |
216 |
regVal &= ~(DLAB_ERF_EN_BIT); //set LCR[7] = 0 -> disable divisor latch mode
|
217 |
|
218 |
//regVal |= dataBits > 3 ? TL16C_WORD_8BITS : wordValues[dataBits]; //set 8bits mode
|
219 |
//regVal |= (stopBit > 1 ? TL16C_STOPBIT_TWO : stopBitValues[stopBit]) << 2; //set stop bits
|
220 |
//regVal |= (parity > 2 ? TL16C_PARITY_EVEN : parityValues[parity]) << 3; //set stop bits
|
221 |
regVal |= dataBits; //set 8bits mode
|
222 |
regVal |= stopBit << 2; //set stop bits |
223 |
regVal |= parity << 3; //set stop bits |
224 |
writePortA(regVal, LCR_REG); |
225 |
//_delay_ms(1);
|
226 |
setWait(20);
|
227 |
writePortA(0x01, FCR_REG); //enable FIFO |
228 |
setWait(20);
|
229 |
} |
230 |
|
231 |
|
232 |
void initPortB(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit)
|
233 |
{ |
234 |
|
235 |
uint8_t regVal = 0; //temp value for reading register and change it's value without clearing it |
236 |
//void (*callFuncWR)();
|
237 |
//uint8_t (*callFuncRD)();
|
238 |
//uint16_t addrWriteFunc[] = {&writePortA, &writePortB, &writePortC, &writePortD};
|
239 |
//uint16_t addrReadFunc[] = {&readPortA, &readPortB, &readPortC, &readPortD};
|
240 |
//uint8_t wordValues[] = {TL16C_WORD_5BITS, TL16C_WORD_6BITS, TL16C_WORD_7BITS, TL16C_WORD_8BITS};
|
241 |
//uint8_t baudsValues[] = {DL_9600_BAUDS, DL_19200_BAUDS, DL_38400_BAUDS};
|
242 |
//uint8_t parityValues[] = {TL16C_PARITY_NONE, TL16C_PARITY_ODD, TL16C_PARITY_EVEN};
|
243 |
//uint8_t stopBitValues[] = {TL16C_STOPBIT_ONE, TL16C_STOPBIT_TWO};
|
244 |
|
245 |
//callFuncWR = uart_type > 3 ? writePortD : addrWriteFunc[uart_type];
|
246 |
//callFuncRD = uart_type > 3 ? writePortD : addrReadFunc[uart_type];
|
247 |
|
248 |
|
249 |
//Read register first...
|
250 |
regVal = readPortB(LCR_REG); |
251 |
//_delay_ms(1);
|
252 |
setWait(20);
|
253 |
regVal = DLAB_ERF_EN_BIT; //set LCR[7] = 1 -> enable divisor latch mode
|
254 |
writePortB(regVal, LCR_REG); //switch Mode
|
255 |
//_delay_ms(1);
|
256 |
setWait(20);
|
257 |
//Set bus speed (according of 8MHz OSC. -> DL = Fosc/(16*Fbauds*DIV));
|
258 |
//DIV = 1 or 4 (see TL16C datasheet p.14), we use here DIV = 1
|
259 |
writePortB(0x00, DLH_REG); //Always 0x00 in our cfg... MAX 12MHz |
260 |
//_delay_ms(1);
|
261 |
setWait(20);
|
262 |
//writePortA(busSpeed > 2 ? DL_38400_BAUDS : baudsValues[busSpeed], DLL_REG);
|
263 |
writePortB(busSpeed, DLL_REG); |
264 |
//_delay_ms(1);
|
265 |
setWait(20);
|
266 |
|
267 |
regVal = readPortB(LCR_REG); |
268 |
regVal &= ~(DLAB_ERF_EN_BIT); //set LCR[7] = 0 -> disable divisor latch mode
|
269 |
|
270 |
//regVal |= dataBits > 3 ? TL16C_WORD_8BITS : wordValues[dataBits]; //set 8bits mode
|
271 |
//regVal |= (stopBit > 1 ? TL16C_STOPBIT_TWO : stopBitValues[stopBit]) << 2; //set stop bits
|
272 |
//regVal |= (parity > 2 ? TL16C_PARITY_EVEN : parityValues[parity]) << 3; //set stop bits
|
273 |
regVal |= dataBits; //set 8bits mode
|
274 |
regVal |= stopBit << 2; //set stop bits |
275 |
regVal |= parity << 3; //set stop bits |
276 |
writePortB(regVal, LCR_REG); |
277 |
//_delay_ms(1);
|
278 |
setWait(20);
|
279 |
writePortB(0x01, FCR_REG); //enable FIFO |
280 |
setWait(20);
|
281 |
} |
282 |
|
283 |
|
284 |
void initPortC(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit)
|
285 |
{ |
286 |
uint8_t regVal = 0; //temp value for reading register and change it's value without clearing it |
287 |
//void (*callFuncWR)();
|
288 |
//uint8_t (*callFuncRD)();
|
289 |
//uint16_t addrWriteFunc[] = {&writePortA, &writePortB, &writePortC, &writePortD};
|
290 |
//uint16_t addrReadFunc[] = {&readPortA, &readPortB, &readPortC, &readPortD};
|
291 |
//uint8_t wordValues[] = {TL16C_WORD_5BITS, TL16C_WORD_6BITS, TL16C_WORD_7BITS, TL16C_WORD_8BITS};
|
292 |
//uint8_t baudsValues[] = {DL_9600_BAUDS, DL_19200_BAUDS, DL_38400_BAUDS};
|
293 |
//uint8_t parityValues[] = {TL16C_PARITY_NONE, TL16C_PARITY_ODD, TL16C_PARITY_EVEN};
|
294 |
//uint8_t stopBitValues[] = {TL16C_STOPBIT_ONE, TL16C_STOPBIT_TWO};
|
295 |
|
296 |
//callFuncWR = uart_type > 3 ? writePortD : addrWriteFunc[uart_type];
|
297 |
//callFuncRD = uart_type > 3 ? writePortD : addrReadFunc[uart_type];
|
298 |
|
299 |
|
300 |
//Read register first...
|
301 |
regVal = readPortC(LCR_REG); |
302 |
//_delay_ms(1);
|
303 |
setWait(20);
|
304 |
regVal = DLAB_ERF_EN_BIT; //set LCR[7] = 1 -> enable divisor latch mode
|
305 |
writePortC(regVal, LCR_REG); //switch Mode
|
306 |
//_delay_ms(1);
|
307 |
setWait(20);
|
308 |
//Set bus speed (according of 8MHz OSC. -> DL = Fosc/(16*Fbauds*DIV));
|
309 |
//DIV = 1 or 4 (see TL16C datasheet p.14), we use here DIV = 1
|
310 |
writePortC(0x00, DLH_REG); //Always 0x00 in our cfg... MAX 12MHz |
311 |
//_delay_ms(1);
|
312 |
setWait(20);
|
313 |
//writePortA(busSpeed > 2 ? DL_38400_BAUDS : baudsValues[busSpeed], DLL_REG);
|
314 |
writePortC(busSpeed, DLL_REG); |
315 |
//_delay_ms(1);
|
316 |
setWait(20);
|
317 |
|
318 |
regVal = readPortC(LCR_REG); |
319 |
regVal &= ~(DLAB_ERF_EN_BIT); //set LCR[7] = 0 -> disable divisor latch mode
|
320 |
|
321 |
//regVal |= dataBits > 3 ? TL16C_WORD_8BITS : wordValues[dataBits]; //set 8bits mode
|
322 |
//regVal |= (stopBit > 1 ? TL16C_STOPBIT_TWO : stopBitValues[stopBit]) << 2; //set stop bits
|
323 |
//regVal |= (parity > 2 ? TL16C_PARITY_EVEN : parityValues[parity]) << 3; //set stop bits
|
324 |
regVal |= dataBits; //set 8bits mode
|
325 |
regVal |= stopBit << 2; //set stop bits |
326 |
regVal |= parity << 3; //set stop bits |
327 |
writePortC(regVal, LCR_REG); |
328 |
//_delay_ms(1);
|
329 |
setWait(20);
|
330 |
writePortC(0x01, FCR_REG); //enable FIFO |
331 |
setWait(20);
|
332 |
} |
333 |
|
334 |
|
335 |
|
336 |
void initPortD(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit)
|
337 |
{ |
338 |
uint8_t regVal = 0; //temp value for reading register and change it's value without clearing it |
339 |
//void (*callFuncWR)();
|
340 |
//uint8_t (*callFuncRD)();
|
341 |
//uint16_t addrWriteFunc[] = {&writePortA, &writePortB, &writePortC, &writePortD};
|
342 |
//uint16_t addrReadFunc[] = {&readPortA, &readPortB, &readPortC, &readPortD};
|
343 |
//uint8_t wordValues[] = {TL16C_WORD_5BITS, TL16C_WORD_6BITS, TL16C_WORD_7BITS, TL16C_WORD_8BITS};
|
344 |
//uint8_t baudsValues[] = {DL_9600_BAUDS, DL_19200_BAUDS, DL_38400_BAUDS};
|
345 |
//uint8_t parityValues[] = {TL16C_PARITY_NONE, TL16C_PARITY_ODD, TL16C_PARITY_EVEN};
|
346 |
//uint8_t stopBitValues[] = {TL16C_STOPBIT_ONE, TL16C_STOPBIT_TWO};
|
347 |
|
348 |
//callFuncWR = uart_type > 3 ? writePortD : addrWriteFunc[uart_type];
|
349 |
//callFuncRD = uart_type > 3 ? writePortD : addrReadFunc[uart_type];
|
350 |
|
351 |
|
352 |
//Read register first...
|
353 |
regVal = readPortD(LCR_REG); |
354 |
//_delay_ms(1);
|
355 |
setWait(20);
|
356 |
regVal = DLAB_ERF_EN_BIT; //set LCR[7] = 1 -> enable divisor latch mode
|
357 |
writePortD(regVal, LCR_REG); //switch Mode (and clear default cfg...)
|
358 |
//_delay_ms(1);
|
359 |
setWait(20);
|
360 |
//Set bus speed (according of 8MHz OSC. -> DL = Fosc/(16*Fbauds*DIV));
|
361 |
//DIV = 1 or 4 (see TL16C datasheet p.14), we use here DIV = 1
|
362 |
writePortD(0x00, DLH_REG); //Always 0x00 in our cfg... MAX 12MHz |
363 |
//_delay_ms(1);
|
364 |
setWait(20);
|
365 |
//writePortA(busSpeed > 2 ? DL_38400_BAUDS : baudsValues[busSpeed], DLL_REG);
|
366 |
writePortD(busSpeed, DLL_REG); |
367 |
//_delay_ms(1);
|
368 |
setWait(20);
|
369 |
|
370 |
regVal = readPortD(LCR_REG); |
371 |
regVal &= ~(DLAB_ERF_EN_BIT); //set LCR[7] = 0 -> disable divisor latch mode
|
372 |
|
373 |
//regVal |= dataBits > 3 ? TL16C_WORD_8BITS : wordValues[dataBits]; //set 8bits mode
|
374 |
//regVal |= (stopBit > 1 ? TL16C_STOPBIT_TWO : stopBitValues[stopBit]) << 2; //set stop bits
|
375 |
//regVal |= (parity > 2 ? TL16C_PARITY_EVEN : parityValues[parity]) << 3; //set stop bits
|
376 |
regVal |= dataBits; //set 8bits mode
|
377 |
regVal |= stopBit << 2; //set stop bits |
378 |
regVal |= parity << 3; //set stop bits |
379 |
writePortD(regVal, LCR_REG); |
380 |
//_delay_ms(1);
|
381 |
setWait(20);
|
382 |
writePortD(0x01, FCR_REG); //enable FIFO |
383 |
setWait(20);
|
384 |
} |
385 |
|
386 |
|
387 |
|
388 |
//////////////////////////////////////////////
|
389 |
//UART send/reiceive
|
390 |
|
391 |
void txWriteA(uint8_t b)
|
392 |
{ |
393 |
writePortA(b, THR_REG); //write to Transmit Holding (that goes into TX FIFO buffer)
|
394 |
} |
395 |
|
396 |
|
397 |
void txWriteB(uint8_t b)
|
398 |
{ |
399 |
writePortB(b, THR_REG); //write to Transmit Holding (that goes into TX FIFO buffer)
|
400 |
} |
401 |
|
402 |
|
403 |
void txWriteC(uint8_t b)
|
404 |
{ |
405 |
writePortC(b, THR_REG); //write to Transmit Holding (that goes into TX FIFO buffer)
|
406 |
} |
407 |
|
408 |
|
409 |
void txWriteD(uint8_t b)
|
410 |
{ |
411 |
writePortD(b, THR_REG); //write to Transmit Holding (that goes into TX FIFO buffer)
|
412 |
} |
413 |
|
414 |
|
415 |
|
416 |
uint8_t rxReadA(void)
|
417 |
{ |
418 |
return readPortA(RHR_REG); //read Receive Holding (from RX FIFO buffer) |
419 |
} |
420 |
|
421 |
|
422 |
uint8_t rxReadB(void)
|
423 |
{ |
424 |
return readPortB(RHR_REG); //read Receive Holding (from RX FIFO buffer) |
425 |
} |
426 |
|
427 |
|
428 |
uint8_t rxReadC(void)
|
429 |
{ |
430 |
return readPortC(RHR_REG); //read Receive Holding (from RX FIFO buffer) |
431 |
} |
432 |
|
433 |
|
434 |
uint8_t rxReadD(void)
|
435 |
{ |
436 |
return readPortD(RHR_REG); //read Receive Holding (from RX FIFO buffer) |
437 |
} |
438 |
|
439 |
|
440 |
////////////////////////////////////////
|
441 |
//RX buf state functions
|
442 |
|
443 |
bool portA_available()
|
444 |
{ |
445 |
return (readPortA(LSR_REG) & 0x01); //check if RX FIFO buffer has at least one byte available |
446 |
} |
447 |
|
448 |
|
449 |
bool portB_available()
|
450 |
{ |
451 |
return (readPortB(LSR_REG) & 0x01); //check if RX FIFO buffer has at least one byte available |
452 |
} |
453 |
|
454 |
|
455 |
bool portC_available()
|
456 |
{ |
457 |
return (readPortC(LSR_REG) & 0x01); //check if RX FIFO buffer has at least one byte available |
458 |
} |
459 |
|
460 |
|
461 |
bool portD_available()
|
462 |
{ |
463 |
return (readPortD(LSR_REG) & 0x01); //check if RX FIFO buffer has at least one byte available |
464 |
} |
465 |
|
466 |
|
467 |
|
468 |
|
469 |
|
470 |
|
471 |
|
472 |
///////////////////////////////////////////////////////
|
473 |
//write functions
|
474 |
|
475 |
|
476 |
|
477 |
void writePortA(uint8_t reg, uint8_t addr)
|
478 |
{ |
479 |
DATADIR(0xFF); //set I/O on write mode |
480 |
ADDRWRITE(addr); //search uartn register
|
481 |
DATAWRITE(reg); //write data
|
482 |
CLRCSA; //enable uartA call
|
483 |
setWait(3);
|
484 |
CLRWR; //enable write mode
|
485 |
setWait(3);
|
486 |
SETWR; //disable write mode
|
487 |
setWait(3);
|
488 |
SETCSA; //disable uartA call
|
489 |
DATADIR(0x00); //set input mode (to reduce power consumption) |
490 |
} |
491 |
|
492 |
void writePortB(uint8_t reg, uint8_t addr)
|
493 |
{ |
494 |
DATADIR(0xFF); //set I/O on write mode |
495 |
ADDRWRITE(addr); //search uartn register
|
496 |
DATAWRITE(reg); //write data
|
497 |
CLRCSB; //enable uartA call
|
498 |
setWait(3);
|
499 |
CLRWR; //enable write mode
|
500 |
setWait(3);
|
501 |
SETWR; //disable write mode
|
502 |
setWait(3);
|
503 |
SETCSB; //disable uartA call
|
504 |
DATADIR(0x00); //set input mode (to reduce power consumption) |
505 |
} |
506 |
|
507 |
void writePortC(uint8_t reg, uint8_t addr)
|
508 |
{ |
509 |
DATADIR(0xFF); //set I/O on write mode |
510 |
ADDRWRITE(addr); //search uartn register
|
511 |
DATAWRITE(reg); //write data
|
512 |
CLRCSC; //enable uartA call
|
513 |
setWait(3);
|
514 |
CLRWR; //enable write mode
|
515 |
setWait(3);
|
516 |
SETWR; //disable write mode
|
517 |
setWait(3);
|
518 |
SETCSC; //disable uartA call
|
519 |
DATADIR(0x00); //set input mode (to reduce power consumption) |
520 |
} |
521 |
|
522 |
void writePortD(uint8_t reg, uint8_t addr)
|
523 |
{ |
524 |
DATADIR(0xFF); //set I/O on write mode |
525 |
ADDRWRITE(addr); //search uartn register
|
526 |
DATAWRITE(reg); //write data
|
527 |
CLRCSD; //enable uartA call
|
528 |
setWait(3);
|
529 |
CLRWR; //enable write mode
|
530 |
setWait(3);
|
531 |
SETWR; //disable write mode
|
532 |
setWait(3);
|
533 |
SETCSD; //disable uartA call
|
534 |
DATADIR(0x00); //set input mode (to reduce power consumption) |
535 |
} |
536 |
|
537 |
|
538 |
///////////////////////////////////////////////////////
|
539 |
//read functions
|
540 |
|
541 |
|
542 |
uint8_t readPortA(uint8_t addr) |
543 |
{ |
544 |
uint8_t result; |
545 |
DATADIR(0x00); //set I/O on read mode |
546 |
ADDRWRITE(addr); //search uartn register
|
547 |
CLRCSA; //enable uartA call
|
548 |
setWait(3);
|
549 |
CLRRD; //enable read mode
|
550 |
setWait(3);
|
551 |
result = PORTD.IN; //set I/O on read mode
|
552 |
setWait(3);
|
553 |
SETRD; //disable read mode
|
554 |
setWait(3);
|
555 |
SETCSA; //hang up uartA call
|
556 |
return result;
|
557 |
} |
558 |
|
559 |
uint8_t readPortB(uint8_t addr) |
560 |
{ |
561 |
uint8_t result; |
562 |
DATADIR(0x00); //set I/O on read mode |
563 |
ADDRWRITE(addr); //search uartn register
|
564 |
CLRCSB; //enable uartB call
|
565 |
setWait(3);
|
566 |
CLRRD; //enable read mode
|
567 |
setWait(3);
|
568 |
result = PORTD.IN; //set I/O on read mode
|
569 |
setWait(3);
|
570 |
SETRD; //disable read mode
|
571 |
setWait(3);
|
572 |
SETCSB; //hang up uartB call
|
573 |
return result;
|
574 |
} |
575 |
|
576 |
uint8_t readPortC(uint8_t addr) |
577 |
{ |
578 |
uint8_t result; |
579 |
DATADIR(0x00); //set I/O on read mode |
580 |
ADDRWRITE(addr); //search uartn register
|
581 |
CLRCSC; //enable uartC call
|
582 |
setWait(3);
|
583 |
CLRRD; //enable read mode
|
584 |
setWait(3);
|
585 |
result = PORTD.IN; //set I/O on read mode
|
586 |
setWait(3);
|
587 |
SETRD; //disable read mode
|
588 |
setWait(3);
|
589 |
SETCSC; //hang up uartC call
|
590 |
return result;
|
591 |
} |
592 |
|
593 |
uint8_t readPortD(uint8_t addr) |
594 |
{ |
595 |
uint8_t result; |
596 |
DATADIR(0x00); //set I/O on read mode |
597 |
ADDRWRITE(addr); //search uartn register
|
598 |
CLRCSD; //enable uartD call
|
599 |
setWait(3);
|
600 |
CLRRD; //enable read mode
|
601 |
setWait(3);
|
602 |
result = PORTD.IN; //set I/O on read mode
|
603 |
setWait(3);
|
604 |
SETRD; //disable read mode
|
605 |
setWait(3);
|
606 |
SETCSD; //hang up uartD call
|
607 |
return result;
|
608 |
} |
609 |
|
610 |
|
611 |
|
612 |
|
613 |
|
614 |
///////////////////////////////////////////
|
615 |
//Miscellaneous functions
|
616 |
|
617 |
void setWait(uint16_t cnt)
|
618 |
{ |
619 |
uint16_t k = 0;
|
620 |
while(k < cnt)
|
621 |
{ |
622 |
asm("nop"); |
623 |
k++; |
624 |
} |
625 |
} |
626 |
|
627 |
|
628 |
|
629 |
|
630 |
|
631 |
#endif /* XC_HEADER_TEMPLATE_H */ |
632 |
|