root / Version 1.6 / RS232_MUX.X / hardware_TL16C754C.h @ 0e6cfafc
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1 | 0e6cfafc | Enzo Niro | /* Microchip Technology Inc. and its subsidiaries. You may use this software
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2 | * and any derivatives exclusively with Microchip products.
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3 | *
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4 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER
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5 | * EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED
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6 | * WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A
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7 | * PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP PRODUCTS, COMBINATION
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8 | * WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
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9 | *
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10 | * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
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11 | * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
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12 | * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
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13 | * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE
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14 | * FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS
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15 | * IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF
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16 | * ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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17 | *
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18 | * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE OF THESE
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19 | * TERMS.
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20 | */
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21 | |||
22 | /*
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23 | * File: hardware_TL16C754C.h
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24 | * Author: Enzo Niro
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25 | * Comments: Library for MUX232 to handle TL16C754C chip
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26 | * Revision history: 1.6
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27 | */
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28 | |||
29 | |||
30 | #ifndef RS232_HARDWARETL16_H
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31 | #define RS232_HARDWARETL16_H
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32 | |||
33 | #include <xc.h> // include processor files - each processor file is guarded. |
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34 | #include "hardware_config.h" |
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35 | |||
36 | |||
37 | |||
38 | //////////////////////////////////////
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39 | //prototypes functions
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40 | |||
41 | |||
42 | //////////////////////////
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43 | //High level functions
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44 | |||
45 | void initPortA(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit);
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46 | void initPortB(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit);
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47 | void initPortC(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit);
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48 | void initPortD(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit);
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49 | |||
50 | //Send bytes throught serial port
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51 | void txWriteA(uint8_t b);
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52 | void txWriteB(uint8_t b);
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53 | void txWriteC(uint8_t b);
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54 | void txWriteD(uint8_t b);
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55 | |||
56 | //Receive bytes from serial port
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57 | uint8_t rxReadA(void);
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58 | uint8_t rxReadB(void);
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59 | uint8_t rxReadC(void);
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60 | uint8_t rxReadD(void);
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61 | |||
62 | //RX buffer control
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63 | |||
64 | //available functions
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65 | bool portA_available();
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66 | bool portB_available();
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67 | bool portC_available();
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68 | bool portD_available();
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69 | |||
70 | //parity functions
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71 | |||
72 | bool getParitySetA();
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73 | bool getParitySetB();
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74 | bool getParitySetC();
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75 | bool getParitySetD();
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76 | |||
77 | /*
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78 |
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79 | TODO : Implement functions...
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80 |
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81 | */
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82 | |||
83 | |||
84 | //////////////////////////
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85 | //Low level functions
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86 | |||
87 | |||
88 | void writePortA(uint8_t reg, uint8_t addr);
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89 | void writePortB(uint8_t reg, uint8_t addr);
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90 | void writePortC(uint8_t reg, uint8_t addr);
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91 | void writePortD(uint8_t reg, uint8_t addr);
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92 | uint8_t readPortA(uint8_t addr); |
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93 | uint8_t readPortB(uint8_t addr); |
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94 | uint8_t readPortC(uint8_t addr); |
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95 | uint8_t readPortD(uint8_t addr); |
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96 | |||
97 | |||
98 | void setWait(uint16_t cnt); //fast delay |
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99 | |||
100 | |||
101 | //////////////////////////////////////////////////////////
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102 | //Values definitions (not supposed to use it directly)
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103 | |||
104 | #define DLAB_ERF_EN_BIT 0x80 |
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105 | |||
106 | |||
107 | #define LCR_REG 0x3 //Static register |
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108 | |||
109 | ///////////////////////////////////////////
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110 | // READ Registers
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111 | |||
112 | #define RHR_REG 0x0 |
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113 | #define IIR_REG 0x2 |
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114 | #define LSR_REG 0x5 |
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115 | #define MSR_REG 0x6 |
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116 | #define FIFORDY_REG 0x7 |
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117 | |||
118 | ///////////////////////////////////////////
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119 | // WRITE Registers
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120 | |||
121 | #define THR_REG 0x0 |
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122 | #define FCR_REG 0x2 |
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123 | |||
124 | ///////////////////////////////////////////
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125 | // READ/WRITE Registers
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126 | |||
127 | #define IER_REG 0x1 |
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128 | #define LCR_REG 0x3 |
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129 | #define MCR_REG 0x4 |
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130 | #define SPR_REG 0x7 |
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131 | #define DLL_REG 0x0 |
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132 | #define DLH_REG 0x1 |
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133 | #define EFR_REG 0x2 |
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134 | #define XON1_REG 0x4 |
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135 | #define XON2_REG 0x5 |
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136 | #define XOFF1_REG 0x6 |
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137 | #define XOFF2_REG 0x7 |
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138 | #define TCR_REG 0x6 |
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139 | #define TLR_REG 0x7 |
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140 | |||
141 | |||
142 | |||
143 | |||
144 | ///////////////////////////////////////////////////////
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145 | //CTRL, ADDR and DATA buses
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146 | |||
147 | //Data pins
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148 | #define DATAWRITE(x) PORTD.OUT = x
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149 | #define DATADIR(x) PORTD.DIR = x
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150 | #define DATAREAD PORTD.IN
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151 | |||
152 | //Address pins
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153 | #define ADDRWRITE(x) PORTE.OUT = x
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154 | #define ADDR_ENABLE PORTE.DIR |= 0x07 |
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155 | |||
156 | |||
157 | //Controls pins
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158 | #define ENABLE_POW_SUPPLY_PIN PORTF.DIR |= 0x01 |
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159 | #define ENABLE_WR_RD_PINS PORTB.DIR |= 0x30 |
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160 | #define ENABLE_CS_PINS PORTB.DIR |= 0x0F |
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161 | #define ENABLE_RESET_PIN PORTE.DIR |= 0x08 |
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162 | #define POWER_ON PORTF.OUT |= 0x01 |
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163 | #define POWER_OFF PORTF.OUT &= ~(0x01) |
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164 | #define SETRST PORTE.OUT |= 0x08 |
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165 | #define SETWR PORTB.OUT |= 0x10 |
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166 | #define SETRD PORTB.OUT |= 0x20 |
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167 | #define SETCSA PORTB.OUT |= 0x01 |
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168 | #define SETCSB PORTB.OUT |= 0x02 |
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169 | #define SETCSC PORTB.OUT |= 0x04 |
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170 | #define SETCSD PORTB.OUT |= 0x08 |
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171 | #define CLRRST PORTE.OUT &= ~(0x08) |
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172 | #define CLRWR PORTB.OUT &= ~(0x10) |
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173 | #define CLRRD PORTB.OUT &= ~(0x20) |
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174 | #define CLRCSA PORTB.OUT &= ~(0x01) |
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175 | #define CLRCSB PORTB.OUT &= ~(0x02) |
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176 | #define CLRCSC PORTB.OUT &= ~(0x04) |
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177 | #define CLRCSD PORTB.OUT &= ~(0x08) |
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178 | |||
179 | |||
180 | ///////////////////////////////////////////////////////////////////////////////
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181 | //Private vars
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182 | |||
183 | bool _portA_parity_set;
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184 | bool _portB_parity_set;
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185 | bool _portC_parity_set;
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186 | bool _portD_parity_set;
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187 | |||
188 | |||
189 | |||
190 | ///////////////////////////////////////////////////////////////////////////////
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191 | //Functions
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192 | |||
193 | //////////////////////////////////////
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194 | //High level functions
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195 | |||
196 | void initPortA(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit)
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197 | { |
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198 | |||
199 | uint16_t speedCfg[] = { DL_9600_BAUDS, DL_19200_BAUDS, DL_38400_BAUDS }; |
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200 | uint8_t parityCfg[] = { TL16C_NO_PARITY, TL16C_EVEN_PARITY, TL16C_ODD_PARITY }; |
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201 | uint8_t dataCfg[] = { F5BIT_MODE, F6BIT_MODE, F7BIT_MODE, F8BIT_MODE }; |
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202 | uint8_t stopCfg[] = { ONE_STOPBIT, TWO_STOPBITS }; |
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203 | |||
204 | |||
205 | uint8_t regVal = 0; //temp value for reading register and change it's value without clearing it |
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206 | |||
207 | _portA_parity_set = (parity > 0); //Parity set (even or odd) ? |
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208 | |||
209 | |||
210 | //Read register first...
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211 | regVal = readPortA(LCR_REG); |
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212 | //_delay_ms(1);
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213 | setWait(20);
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214 | regVal = DLAB_ERF_EN_BIT; //set LCR[7] = 1 -> enable divisor latch mode
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215 | writePortA(regVal, LCR_REG); //switch Mode
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216 | //_delay_ms(1);
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217 | setWait(20);
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218 | //Set bus speed (according of 8MHz OSC. -> DL = Fosc/(16*Fbauds*DIV));
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219 | //DIV = 1 or 4 (see TL16C datasheet p.14), we use here DIV = 1
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220 | writePortA(0x00, DLH_REG); //Always 0x00 in our cfg... MAX 12MHz |
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221 | //_delay_ms(1);
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222 | setWait(20);
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223 | //writePortA(busSpeed > 2 ? DL_38400_BAUDS : baudsValues[busSpeed], DLL_REG);
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224 | writePortA(speedCfg[busSpeed], DLL_REG); |
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225 | //_delay_ms(1);
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226 | setWait(20);
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227 | |||
228 | regVal = readPortA(LCR_REG); |
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229 | regVal &= ~(DLAB_ERF_EN_BIT); //set LCR[7] = 0 -> disable divisor latch mode
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230 | |||
231 | //regVal |= dataBits > 3 ? TL16C_WORD_8BITS : wordValues[dataBits]; //set 8bits mode
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232 | //regVal |= (stopBit > 1 ? TL16C_STOPBIT_TWO : stopBitValues[stopBit]) << 2; //set stop bits
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233 | //regVal |= (parity > 2 ? TL16C_PARITY_EVEN : parityValues[parity]) << 3; //set stop bits
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234 | regVal |= dataCfg[dataBits]; //set 8bits mode
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235 | regVal |= stopCfg[stopBit] << 2; //set stop bits |
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236 | regVal |= parityCfg[parity] << 3; //set stop bits |
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237 | writePortA(regVal, LCR_REG); |
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238 | //_delay_ms(1);
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239 | setWait(20);
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240 | writePortA(0x01, FCR_REG); //enable FIFO |
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241 | setWait(20);
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242 | } |
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243 | |||
244 | |||
245 | void initPortB(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit)
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246 | { |
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247 | |||
248 | uint16_t speedCfg[] = { DL_9600_BAUDS, DL_19200_BAUDS, DL_38400_BAUDS }; |
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249 | uint8_t parityCfg[] = { TL16C_NO_PARITY, TL16C_EVEN_PARITY, TL16C_ODD_PARITY }; |
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250 | uint8_t dataCfg[] = { F5BIT_MODE, F6BIT_MODE, F7BIT_MODE, F8BIT_MODE }; |
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251 | uint8_t stopCfg[] = { ONE_STOPBIT, TWO_STOPBITS }; |
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252 | |||
253 | |||
254 | uint8_t regVal = 0; //temp value for reading register and change it's value without clearing it |
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255 | |||
256 | _portB_parity_set = (parity > 0); //Parity set (even or odd) ? |
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257 | |||
258 | |||
259 | //Read register first...
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260 | regVal = readPortB(LCR_REG); |
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261 | //_delay_ms(1);
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262 | setWait(20);
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263 | regVal = DLAB_ERF_EN_BIT; //set LCR[7] = 1 -> enable divisor latch mode
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264 | writePortB(regVal, LCR_REG); //switch Mode
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265 | //_delay_ms(1);
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266 | setWait(20);
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267 | //Set bus speed (according of 8MHz OSC. -> DL = Fosc/(16*Fbauds*DIV));
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268 | //DIV = 1 or 4 (see TL16C datasheet p.14), we use here DIV = 1
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269 | writePortB(0x00, DLH_REG); //Always 0x00 in our cfg... MAX 12MHz |
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270 | //_delay_ms(1);
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271 | setWait(20);
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272 | //writePortA(busSpeed > 2 ? DL_38400_BAUDS : baudsValues[busSpeed], DLL_REG);
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273 | writePortB(speedCfg[busSpeed], DLL_REG); |
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274 | //_delay_ms(1);
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275 | setWait(20);
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276 | |||
277 | regVal = readPortB(LCR_REG); |
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278 | regVal &= ~(DLAB_ERF_EN_BIT); //set LCR[7] = 0 -> disable divisor latch mode
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279 | |||
280 | //regVal |= dataBits > 3 ? TL16C_WORD_8BITS : wordValues[dataBits]; //set 8bits mode
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281 | //regVal |= (stopBit > 1 ? TL16C_STOPBIT_TWO : stopBitValues[stopBit]) << 2; //set stop bits
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282 | //regVal |= (parity > 2 ? TL16C_PARITY_EVEN : parityValues[parity]) << 3; //set stop bits
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283 | regVal |= dataCfg[dataBits]; //set 8bits mode
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284 | regVal |= stopCfg[stopBit] << 2; //set stop bits |
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285 | regVal |= parityCfg[parity] << 3; //set stop bits |
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286 | writePortB(regVal, LCR_REG); |
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287 | //_delay_ms(1);
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288 | setWait(20);
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289 | writePortB(0x01, FCR_REG); //enable FIFO |
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290 | setWait(20);
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291 | } |
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292 | |||
293 | |||
294 | void initPortC(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit)
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295 | { |
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296 | |||
297 | uint16_t speedCfg[] = { DL_9600_BAUDS, DL_19200_BAUDS, DL_38400_BAUDS }; |
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298 | uint8_t parityCfg[] = { TL16C_NO_PARITY, TL16C_EVEN_PARITY, TL16C_ODD_PARITY }; |
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299 | uint8_t dataCfg[] = { F5BIT_MODE, F6BIT_MODE, F7BIT_MODE, F8BIT_MODE }; |
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300 | uint8_t stopCfg[] = { ONE_STOPBIT, TWO_STOPBITS }; |
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301 | |||
302 | uint8_t regVal = 0; //temp value for reading register and change it's value without clearing it |
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303 | |||
304 | _portC_parity_set = (parity > 0); //Parity set (even or odd) ? |
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305 | |||
306 | |||
307 | //Read register first...
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308 | regVal = readPortC(LCR_REG); |
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309 | //_delay_ms(1);
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310 | setWait(20);
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311 | regVal = DLAB_ERF_EN_BIT; //set LCR[7] = 1 -> enable divisor latch mode
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312 | writePortC(regVal, LCR_REG); //switch Mode
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313 | //_delay_ms(1);
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314 | setWait(20);
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315 | //Set bus speed (according of 8MHz OSC. -> DL = Fosc/(16*Fbauds*DIV));
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316 | //DIV = 1 or 4 (see TL16C datasheet p.14), we use here DIV = 1
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317 | writePortC(0x00, DLH_REG); //Always 0x00 in our cfg... MAX 12MHz |
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318 | //_delay_ms(1);
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319 | setWait(20);
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320 | //writePortA(busSpeed > 2 ? DL_38400_BAUDS : baudsValues[busSpeed], DLL_REG);
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321 | writePortC(speedCfg[busSpeed], DLL_REG); |
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322 | //_delay_ms(1);
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323 | setWait(20);
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324 | |||
325 | regVal = readPortC(LCR_REG); |
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326 | regVal &= ~(DLAB_ERF_EN_BIT); //set LCR[7] = 0 -> disable divisor latch mode
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327 | |||
328 | //regVal |= dataBits > 3 ? TL16C_WORD_8BITS : wordValues[dataBits]; //set 8bits mode
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329 | //regVal |= (stopBit > 1 ? TL16C_STOPBIT_TWO : stopBitValues[stopBit]) << 2; //set stop bits
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330 | //regVal |= (parity > 2 ? TL16C_PARITY_EVEN : parityValues[parity]) << 3; //set stop bits
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331 | regVal |= dataCfg[dataBits]; //set 8bits mode
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332 | regVal |= stopCfg[stopBit] << 2; //set stop bits |
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333 | regVal |= parityCfg[parity] << 3; //set stop bits |
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334 | writePortC(regVal, LCR_REG); |
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335 | //_delay_ms(1);
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336 | setWait(20);
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337 | writePortC(0x01, FCR_REG); //enable FIFO |
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338 | setWait(20);
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339 | } |
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340 | |||
341 | |||
342 | |||
343 | void initPortD(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit)
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344 | { |
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345 | |||
346 | uint16_t speedCfg[] = { DL_9600_BAUDS, DL_19200_BAUDS, DL_38400_BAUDS }; |
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347 | uint8_t parityCfg[] = { TL16C_NO_PARITY, TL16C_EVEN_PARITY, TL16C_ODD_PARITY }; |
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348 | uint8_t dataCfg[] = { F5BIT_MODE, F6BIT_MODE, F7BIT_MODE, F8BIT_MODE }; |
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349 | uint8_t stopCfg[] = { ONE_STOPBIT, TWO_STOPBITS }; |
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350 | |||
351 | uint8_t regVal = 0; //temp value for reading register and change it's value without clearing it |
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352 | |||
353 | _portD_parity_set = (parity > 0); //Parity set (even or odd) ? |
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354 | |||
355 | |||
356 | //Read register first...
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357 | regVal = readPortD(LCR_REG); |
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358 | //_delay_ms(1);
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359 | setWait(20);
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360 | regVal = DLAB_ERF_EN_BIT; //set LCR[7] = 1 -> enable divisor latch mode
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361 | writePortD(regVal, LCR_REG); //switch Mode (and clear default cfg...)
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362 | //_delay_ms(1);
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363 | setWait(20);
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364 | //Set bus speed (according of 8MHz OSC. -> DL = Fosc/(16*Fbauds*DIV));
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365 | //DIV = 1 or 4 (see TL16C datasheet p.14), we use here DIV = 1
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366 | writePortD(0x00, DLH_REG); //Always 0x00 in our cfg... MAX 12MHz |
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367 | //_delay_ms(1);
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368 | setWait(20);
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369 | //writePortA(busSpeed > 2 ? DL_38400_BAUDS : baudsValues[busSpeed], DLL_REG);
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370 | writePortD(speedCfg[busSpeed], DLL_REG); |
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371 | //_delay_ms(1);
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372 | setWait(20);
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373 | |||
374 | regVal = readPortD(LCR_REG); |
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375 | regVal &= ~(DLAB_ERF_EN_BIT); //set LCR[7] = 0 -> disable divisor latch mode
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376 | |||
377 | //regVal |= dataBits > 3 ? TL16C_WORD_8BITS : wordValues[dataBits]; //set 8bits mode
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378 | //regVal |= (stopBit > 1 ? TL16C_STOPBIT_TWO : stopBitValues[stopBit]) << 2; //set stop bits
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379 | //regVal |= (parity > 2 ? TL16C_PARITY_EVEN : parityValues[parity]) << 3; //set stop bits
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380 | regVal |= dataCfg[dataBits]; //set 8bits mode
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381 | regVal |= stopCfg[stopBit] << 2; //set stop bits |
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382 | regVal |= parityCfg[parity] << 3; //set stop bits |
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383 | writePortD(regVal, LCR_REG); |
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384 | //_delay_ms(1);
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385 | setWait(20);
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386 | writePortD(0x01, FCR_REG); //enable FIFO |
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387 | setWait(20);
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388 | } |
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389 | |||
390 | |||
391 | |||
392 | //////////////////////////////////////////////
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393 | //UART send/reiceive
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394 | |||
395 | void txWriteA(uint8_t b)
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396 | { |
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397 | writePortA(b, THR_REG); //write to Transmit Holding (that goes into TX FIFO buffer)
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398 | } |
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399 | |||
400 | |||
401 | void txWriteB(uint8_t b)
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402 | { |
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403 | writePortB(b, THR_REG); //write to Transmit Holding (that goes into TX FIFO buffer)
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404 | } |
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405 | |||
406 | |||
407 | void txWriteC(uint8_t b)
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408 | { |
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409 | writePortC(b, THR_REG); //write to Transmit Holding (that goes into TX FIFO buffer)
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410 | } |
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411 | |||
412 | |||
413 | void txWriteD(uint8_t b)
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414 | { |
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415 | writePortD(b, THR_REG); //write to Transmit Holding (that goes into TX FIFO buffer)
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416 | } |
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417 | |||
418 | |||
419 | |||
420 | uint8_t rxReadA(void)
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421 | { |
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422 | return readPortA(RHR_REG); //read Receive Holding (from RX FIFO buffer) |
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423 | } |
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424 | |||
425 | |||
426 | uint8_t rxReadB(void)
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427 | { |
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428 | return readPortB(RHR_REG); //read Receive Holding (from RX FIFO buffer) |
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429 | } |
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430 | |||
431 | |||
432 | uint8_t rxReadC(void)
|
||
433 | { |
||
434 | return readPortC(RHR_REG); //read Receive Holding (from RX FIFO buffer) |
||
435 | } |
||
436 | |||
437 | |||
438 | uint8_t rxReadD(void)
|
||
439 | { |
||
440 | return readPortD(RHR_REG); //read Receive Holding (from RX FIFO buffer) |
||
441 | } |
||
442 | |||
443 | |||
444 | ////////////////////////////////////////
|
||
445 | //RX buf state functions
|
||
446 | |||
447 | bool portA_available()
|
||
448 | { |
||
449 | return (readPortA(LSR_REG) & 0x01); //check if RX FIFO buffer has at least one byte available |
||
450 | } |
||
451 | |||
452 | |||
453 | bool portB_available()
|
||
454 | { |
||
455 | return (readPortB(LSR_REG) & 0x01); //check if RX FIFO buffer has at least one byte available |
||
456 | } |
||
457 | |||
458 | |||
459 | bool portC_available()
|
||
460 | { |
||
461 | return (readPortC(LSR_REG) & 0x01); //check if RX FIFO buffer has at least one byte available |
||
462 | } |
||
463 | |||
464 | |||
465 | bool portD_available()
|
||
466 | { |
||
467 | return (readPortD(LSR_REG) & 0x01); //check if RX FIFO buffer has at least one byte available |
||
468 | } |
||
469 | |||
470 | |||
471 | ///////////////////////////////////////////////////////////////////////
|
||
472 | //Parity configuration status
|
||
473 | |||
474 | //get status if port has been configured with a parity into the frame
|
||
475 | bool getParitySetA()
|
||
476 | { |
||
477 | return _portA_parity_set;
|
||
478 | } |
||
479 | |||
480 | bool getParitySetB()
|
||
481 | { |
||
482 | return _portB_parity_set;
|
||
483 | } |
||
484 | |||
485 | bool getParitySetC()
|
||
486 | { |
||
487 | return _portC_parity_set;
|
||
488 | } |
||
489 | |||
490 | bool getParitySetD()
|
||
491 | { |
||
492 | return _portD_parity_set;
|
||
493 | } |
||
494 | |||
495 | |||
496 | |||
497 | //Get parity/stopbit error status when frame received on port
|
||
498 | |||
499 | bool getErrorStatusA()
|
||
500 | { |
||
501 | return ((readPortA(LSR_REG) & 0x80) == 0x80); |
||
502 | } |
||
503 | |||
504 | bool getErrorStatusB()
|
||
505 | { |
||
506 | return ((readPortB(LSR_REG) & 0x80) == 0x80); |
||
507 | } |
||
508 | |||
509 | bool getErrorStatusC()
|
||
510 | { |
||
511 | return ((readPortC(LSR_REG) & 0x80) == 0x80); |
||
512 | } |
||
513 | |||
514 | bool getErrorStatusD()
|
||
515 | { |
||
516 | return ((readPortD(LSR_REG) & 0x80) == 0x80); |
||
517 | } |
||
518 | |||
519 | |||
520 | ///////////////////////////////////////////////////////
|
||
521 | //write functions
|
||
522 | |||
523 | |||
524 | |||
525 | void writePortA(uint8_t reg, uint8_t addr)
|
||
526 | { |
||
527 | DATADIR(0xFF); //set I/O on write mode |
||
528 | ADDRWRITE(addr); //search uartn register
|
||
529 | DATAWRITE(reg); //write data
|
||
530 | CLRCSA; //enable uartA call
|
||
531 | setWait(3);
|
||
532 | CLRWR; //enable write mode
|
||
533 | setWait(3);
|
||
534 | SETWR; //disable write mode
|
||
535 | setWait(3);
|
||
536 | SETCSA; //disable uartA call
|
||
537 | DATADIR(0x00); //set input mode (to reduce power consumption) |
||
538 | } |
||
539 | |||
540 | void writePortB(uint8_t reg, uint8_t addr)
|
||
541 | { |
||
542 | DATADIR(0xFF); //set I/O on write mode |
||
543 | ADDRWRITE(addr); //search uartn register
|
||
544 | DATAWRITE(reg); //write data
|
||
545 | CLRCSB; //enable uartA call
|
||
546 | setWait(3);
|
||
547 | CLRWR; //enable write mode
|
||
548 | setWait(3);
|
||
549 | SETWR; //disable write mode
|
||
550 | setWait(3);
|
||
551 | SETCSB; //disable uartA call
|
||
552 | DATADIR(0x00); //set input mode (to reduce power consumption) |
||
553 | } |
||
554 | |||
555 | void writePortC(uint8_t reg, uint8_t addr)
|
||
556 | { |
||
557 | DATADIR(0xFF); //set I/O on write mode |
||
558 | ADDRWRITE(addr); //search uartn register
|
||
559 | DATAWRITE(reg); //write data
|
||
560 | CLRCSC; //enable uartA call
|
||
561 | setWait(3);
|
||
562 | CLRWR; //enable write mode
|
||
563 | setWait(3);
|
||
564 | SETWR; //disable write mode
|
||
565 | setWait(3);
|
||
566 | SETCSC; //disable uartA call
|
||
567 | DATADIR(0x00); //set input mode (to reduce power consumption) |
||
568 | } |
||
569 | |||
570 | void writePortD(uint8_t reg, uint8_t addr)
|
||
571 | { |
||
572 | DATADIR(0xFF); //set I/O on write mode |
||
573 | ADDRWRITE(addr); //search uartn register
|
||
574 | DATAWRITE(reg); //write data
|
||
575 | CLRCSD; //enable uartA call
|
||
576 | setWait(3);
|
||
577 | CLRWR; //enable write mode
|
||
578 | setWait(3);
|
||
579 | SETWR; //disable write mode
|
||
580 | setWait(3);
|
||
581 | SETCSD; //disable uartA call
|
||
582 | DATADIR(0x00); //set input mode (to reduce power consumption) |
||
583 | } |
||
584 | |||
585 | |||
586 | ///////////////////////////////////////////////////////
|
||
587 | //read functions
|
||
588 | |||
589 | |||
590 | uint8_t readPortA(uint8_t addr) |
||
591 | { |
||
592 | uint8_t result; |
||
593 | DATADIR(0x00); //set I/O on read mode |
||
594 | ADDRWRITE(addr); //search uartn register
|
||
595 | CLRCSA; //enable uartA call
|
||
596 | setWait(3);
|
||
597 | CLRRD; //enable read mode
|
||
598 | setWait(3);
|
||
599 | result = PORTD.IN; //set I/O on read mode
|
||
600 | setWait(3);
|
||
601 | SETRD; //disable read mode
|
||
602 | setWait(3);
|
||
603 | SETCSA; //hang up uartA call
|
||
604 | return result;
|
||
605 | } |
||
606 | |||
607 | uint8_t readPortB(uint8_t addr) |
||
608 | { |
||
609 | uint8_t result; |
||
610 | DATADIR(0x00); //set I/O on read mode |
||
611 | ADDRWRITE(addr); //search uartn register
|
||
612 | CLRCSB; //enable uartB call
|
||
613 | setWait(3);
|
||
614 | CLRRD; //enable read mode
|
||
615 | setWait(3);
|
||
616 | result = PORTD.IN; //set I/O on read mode
|
||
617 | setWait(3);
|
||
618 | SETRD; //disable read mode
|
||
619 | setWait(3);
|
||
620 | SETCSB; //hang up uartB call
|
||
621 | return result;
|
||
622 | } |
||
623 | |||
624 | uint8_t readPortC(uint8_t addr) |
||
625 | { |
||
626 | uint8_t result; |
||
627 | DATADIR(0x00); //set I/O on read mode |
||
628 | ADDRWRITE(addr); //search uartn register
|
||
629 | CLRCSC; //enable uartC call
|
||
630 | setWait(3);
|
||
631 | CLRRD; //enable read mode
|
||
632 | setWait(3);
|
||
633 | result = PORTD.IN; //set I/O on read mode
|
||
634 | setWait(3);
|
||
635 | SETRD; //disable read mode
|
||
636 | setWait(3);
|
||
637 | SETCSC; //hang up uartC call
|
||
638 | return result;
|
||
639 | } |
||
640 | |||
641 | uint8_t readPortD(uint8_t addr) |
||
642 | { |
||
643 | uint8_t result; |
||
644 | DATADIR(0x00); //set I/O on read mode |
||
645 | ADDRWRITE(addr); //search uartn register
|
||
646 | CLRCSD; //enable uartD call
|
||
647 | setWait(3);
|
||
648 | CLRRD; //enable read mode
|
||
649 | setWait(3);
|
||
650 | result = PORTD.IN; //set I/O on read mode
|
||
651 | setWait(3);
|
||
652 | SETRD; //disable read mode
|
||
653 | setWait(3);
|
||
654 | SETCSD; //hang up uartD call
|
||
655 | return result;
|
||
656 | } |
||
657 | |||
658 | |||
659 | |||
660 | |||
661 | |||
662 | ///////////////////////////////////////////
|
||
663 | //Miscellaneous functions
|
||
664 | |||
665 | void setWait(uint16_t cnt)
|
||
666 | { |
||
667 | uint16_t k = 0;
|
||
668 | while(k < cnt)
|
||
669 | { |
||
670 | asm("nop"); |
||
671 | k++; |
||
672 | } |
||
673 | } |
||
674 | |||
675 | |||
676 | |||
677 | |||
678 | |||
679 | #endif /* XC_HEADER_TEMPLATE_H */ |