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/* Microchip Technology Inc. and its subsidiaries. You may use this software
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* and any derivatives exclusively with Microchip products.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER
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* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED
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* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A
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* PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP PRODUCTS, COMBINATION
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* WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
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*
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* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
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* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
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* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
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* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE
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* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS
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* IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF
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* ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE OF THESE
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* TERMS.
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*/
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/*
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* File: hardware_TL16C754C.h
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* Author: Enzo Niro
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* Comments: Library for MUX232 to handle TL16C754C chip
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* Revision history: 1.6
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*/
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#ifndef RS232_HARDWARETL16_H
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#define RS232_HARDWARETL16_H
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#include <xc.h> // include processor files - each processor file is guarded. |
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#include "hardware_config.h" |
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//////////////////////////////////////
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//prototypes functions
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//////////////////////////
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//High level functions
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void initPortA(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit);
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void initPortB(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit);
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void initPortC(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit);
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void initPortD(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit);
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//Send bytes throught serial port
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void txWriteA(uint8_t b);
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void txWriteB(uint8_t b);
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void txWriteC(uint8_t b);
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void txWriteD(uint8_t b);
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//Receive bytes from serial port
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uint8_t rxReadA(void);
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uint8_t rxReadB(void);
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uint8_t rxReadC(void);
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uint8_t rxReadD(void);
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//RX buffer control
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//available functions
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bool portA_available();
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bool portB_available();
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bool portC_available();
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bool portD_available();
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//parity functions
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bool getParitySetA();
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bool getParitySetB();
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bool getParitySetC();
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bool getParitySetD();
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/*
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TODO : Implement functions...
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*/
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//////////////////////////
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//Low level functions
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void writePortA(uint8_t reg, uint8_t addr);
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void writePortB(uint8_t reg, uint8_t addr);
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void writePortC(uint8_t reg, uint8_t addr);
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void writePortD(uint8_t reg, uint8_t addr);
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uint8_t readPortA(uint8_t addr); |
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uint8_t readPortB(uint8_t addr); |
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uint8_t readPortC(uint8_t addr); |
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uint8_t readPortD(uint8_t addr); |
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void setWait(uint16_t cnt); //fast delay |
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//////////////////////////////////////////////////////////
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//Values definitions (not supposed to use it directly)
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#define DLAB_ERF_EN_BIT 0x80 |
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#define LCR_REG 0x3 //Static register |
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///////////////////////////////////////////
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// READ Registers
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#define RHR_REG 0x0 |
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#define IIR_REG 0x2 |
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#define LSR_REG 0x5 |
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#define MSR_REG 0x6 |
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#define FIFORDY_REG 0x7 |
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///////////////////////////////////////////
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// WRITE Registers
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#define THR_REG 0x0 |
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#define FCR_REG 0x2 |
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///////////////////////////////////////////
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// READ/WRITE Registers
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#define IER_REG 0x1 |
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#define LCR_REG 0x3 |
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#define MCR_REG 0x4 |
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#define SPR_REG 0x7 |
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#define DLL_REG 0x0 |
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#define DLH_REG 0x1 |
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#define EFR_REG 0x2 |
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#define XON1_REG 0x4 |
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#define XON2_REG 0x5 |
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#define XOFF1_REG 0x6 |
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#define XOFF2_REG 0x7 |
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#define TCR_REG 0x6 |
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#define TLR_REG 0x7 |
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///////////////////////////////////////////////////////
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//CTRL, ADDR and DATA buses
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//Data pins
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#define DATAWRITE(x) PORTD.OUT = x
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#define DATADIR(x) PORTD.DIR = x
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#define DATAREAD PORTD.IN
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//Address pins
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#define ADDRWRITE(x) PORTE.OUT = x
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#define ADDR_ENABLE PORTE.DIR |= 0x07 |
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//Controls pins
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#define ENABLE_POW_SUPPLY_PIN PORTF.DIR |= 0x01 |
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#define ENABLE_WR_RD_PINS PORTB.DIR |= 0x30 |
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#define ENABLE_CS_PINS PORTB.DIR |= 0x0F |
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#define ENABLE_RESET_PIN PORTE.DIR |= 0x08 |
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#define POWER_ON PORTF.OUT |= 0x01 |
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#define POWER_OFF PORTF.OUT &= ~(0x01) |
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#define SETRST PORTE.OUT |= 0x08 |
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#define SETWR PORTB.OUT |= 0x10 |
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#define SETRD PORTB.OUT |= 0x20 |
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#define SETCSA PORTB.OUT |= 0x01 |
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#define SETCSB PORTB.OUT |= 0x02 |
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#define SETCSC PORTB.OUT |= 0x04 |
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#define SETCSD PORTB.OUT |= 0x08 |
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#define CLRRST PORTE.OUT &= ~(0x08) |
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#define CLRWR PORTB.OUT &= ~(0x10) |
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#define CLRRD PORTB.OUT &= ~(0x20) |
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#define CLRCSA PORTB.OUT &= ~(0x01) |
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#define CLRCSB PORTB.OUT &= ~(0x02) |
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#define CLRCSC PORTB.OUT &= ~(0x04) |
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#define CLRCSD PORTB.OUT &= ~(0x08) |
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///////////////////////////////////////////////////////////////////////////////
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//Private vars
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bool _portA_parity_set;
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bool _portB_parity_set;
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bool _portC_parity_set;
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bool _portD_parity_set;
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///////////////////////////////////////////////////////////////////////////////
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//Functions
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//////////////////////////////////////
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//High level functions
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void initPortA(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit)
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{ |
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uint16_t speedCfg[] = { DL_9600_BAUDS, DL_19200_BAUDS, DL_38400_BAUDS }; |
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uint8_t parityCfg[] = { TL16C_NO_PARITY, TL16C_EVEN_PARITY, TL16C_ODD_PARITY }; |
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uint8_t dataCfg[] = { F5BIT_MODE, F6BIT_MODE, F7BIT_MODE, F8BIT_MODE }; |
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uint8_t stopCfg[] = { ONE_STOPBIT, TWO_STOPBITS }; |
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uint8_t regVal = 0; //temp value for reading register and change it's value without clearing it |
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_portA_parity_set = (parity > 0); //Parity set (even or odd) ? |
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//Read register first...
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regVal = readPortA(LCR_REG); |
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//_delay_ms(1);
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setWait(20);
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regVal = DLAB_ERF_EN_BIT; //set LCR[7] = 1 -> enable divisor latch mode
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writePortA(regVal, LCR_REG); //switch Mode
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//_delay_ms(1);
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setWait(20);
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//Set bus speed (according of 8MHz OSC. -> DL = Fosc/(16*Fbauds*DIV));
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//DIV = 1 or 4 (see TL16C datasheet p.14), we use here DIV = 1
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writePortA(0x00, DLH_REG); //Always 0x00 in our cfg... MAX 12MHz |
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//_delay_ms(1);
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setWait(20);
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//writePortA(busSpeed > 2 ? DL_38400_BAUDS : baudsValues[busSpeed], DLL_REG);
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writePortA(speedCfg[busSpeed], DLL_REG); |
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//_delay_ms(1);
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setWait(20);
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regVal = readPortA(LCR_REG); |
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regVal &= ~(DLAB_ERF_EN_BIT); //set LCR[7] = 0 -> disable divisor latch mode
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//regVal |= dataBits > 3 ? TL16C_WORD_8BITS : wordValues[dataBits]; //set 8bits mode
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//regVal |= (stopBit > 1 ? TL16C_STOPBIT_TWO : stopBitValues[stopBit]) << 2; //set stop bits
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//regVal |= (parity > 2 ? TL16C_PARITY_EVEN : parityValues[parity]) << 3; //set stop bits
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regVal |= dataCfg[dataBits]; //set 8bits mode
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regVal |= stopCfg[stopBit] << 2; //set stop bits |
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regVal |= parityCfg[parity] << 3; //set stop bits |
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writePortA(regVal, LCR_REG); |
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//_delay_ms(1);
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setWait(20);
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writePortA(0x01, FCR_REG); //enable FIFO |
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setWait(20);
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} |
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void initPortB(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit)
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{ |
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uint16_t speedCfg[] = { DL_9600_BAUDS, DL_19200_BAUDS, DL_38400_BAUDS }; |
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uint8_t parityCfg[] = { TL16C_NO_PARITY, TL16C_EVEN_PARITY, TL16C_ODD_PARITY }; |
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uint8_t dataCfg[] = { F5BIT_MODE, F6BIT_MODE, F7BIT_MODE, F8BIT_MODE }; |
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uint8_t stopCfg[] = { ONE_STOPBIT, TWO_STOPBITS }; |
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uint8_t regVal = 0; //temp value for reading register and change it's value without clearing it |
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_portB_parity_set = (parity > 0); //Parity set (even or odd) ? |
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//Read register first...
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regVal = readPortB(LCR_REG); |
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//_delay_ms(1);
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setWait(20);
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regVal = DLAB_ERF_EN_BIT; //set LCR[7] = 1 -> enable divisor latch mode
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writePortB(regVal, LCR_REG); //switch Mode
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//_delay_ms(1);
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setWait(20);
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//Set bus speed (according of 8MHz OSC. -> DL = Fosc/(16*Fbauds*DIV));
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//DIV = 1 or 4 (see TL16C datasheet p.14), we use here DIV = 1
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writePortB(0x00, DLH_REG); //Always 0x00 in our cfg... MAX 12MHz |
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//_delay_ms(1);
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setWait(20);
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//writePortA(busSpeed > 2 ? DL_38400_BAUDS : baudsValues[busSpeed], DLL_REG);
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writePortB(speedCfg[busSpeed], DLL_REG); |
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//_delay_ms(1);
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setWait(20);
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regVal = readPortB(LCR_REG); |
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regVal &= ~(DLAB_ERF_EN_BIT); //set LCR[7] = 0 -> disable divisor latch mode
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//regVal |= dataBits > 3 ? TL16C_WORD_8BITS : wordValues[dataBits]; //set 8bits mode
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//regVal |= (stopBit > 1 ? TL16C_STOPBIT_TWO : stopBitValues[stopBit]) << 2; //set stop bits
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//regVal |= (parity > 2 ? TL16C_PARITY_EVEN : parityValues[parity]) << 3; //set stop bits
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regVal |= dataCfg[dataBits]; //set 8bits mode
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regVal |= stopCfg[stopBit] << 2; //set stop bits |
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regVal |= parityCfg[parity] << 3; //set stop bits |
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writePortB(regVal, LCR_REG); |
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//_delay_ms(1);
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setWait(20);
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writePortB(0x01, FCR_REG); //enable FIFO |
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setWait(20);
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} |
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void initPortC(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit)
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{ |
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uint16_t speedCfg[] = { DL_9600_BAUDS, DL_19200_BAUDS, DL_38400_BAUDS }; |
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uint8_t parityCfg[] = { TL16C_NO_PARITY, TL16C_EVEN_PARITY, TL16C_ODD_PARITY }; |
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uint8_t dataCfg[] = { F5BIT_MODE, F6BIT_MODE, F7BIT_MODE, F8BIT_MODE }; |
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uint8_t stopCfg[] = { ONE_STOPBIT, TWO_STOPBITS }; |
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uint8_t regVal = 0; //temp value for reading register and change it's value without clearing it |
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_portC_parity_set = (parity > 0); //Parity set (even or odd) ? |
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//Read register first...
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regVal = readPortC(LCR_REG); |
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//_delay_ms(1);
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setWait(20);
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regVal = DLAB_ERF_EN_BIT; //set LCR[7] = 1 -> enable divisor latch mode
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writePortC(regVal, LCR_REG); //switch Mode
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//_delay_ms(1);
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setWait(20);
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//Set bus speed (according of 8MHz OSC. -> DL = Fosc/(16*Fbauds*DIV));
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//DIV = 1 or 4 (see TL16C datasheet p.14), we use here DIV = 1
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writePortC(0x00, DLH_REG); //Always 0x00 in our cfg... MAX 12MHz |
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//_delay_ms(1);
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setWait(20);
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//writePortA(busSpeed > 2 ? DL_38400_BAUDS : baudsValues[busSpeed], DLL_REG);
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writePortC(speedCfg[busSpeed], DLL_REG); |
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//_delay_ms(1);
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setWait(20);
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regVal = readPortC(LCR_REG); |
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regVal &= ~(DLAB_ERF_EN_BIT); //set LCR[7] = 0 -> disable divisor latch mode
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//regVal |= dataBits > 3 ? TL16C_WORD_8BITS : wordValues[dataBits]; //set 8bits mode
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//regVal |= (stopBit > 1 ? TL16C_STOPBIT_TWO : stopBitValues[stopBit]) << 2; //set stop bits
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//regVal |= (parity > 2 ? TL16C_PARITY_EVEN : parityValues[parity]) << 3; //set stop bits
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regVal |= dataCfg[dataBits]; //set 8bits mode
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regVal |= stopCfg[stopBit] << 2; //set stop bits |
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regVal |= parityCfg[parity] << 3; //set stop bits |
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writePortC(regVal, LCR_REG); |
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//_delay_ms(1);
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setWait(20);
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writePortC(0x01, FCR_REG); //enable FIFO |
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setWait(20);
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} |
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void initPortD(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit)
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{ |
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uint16_t speedCfg[] = { DL_9600_BAUDS, DL_19200_BAUDS, DL_38400_BAUDS }; |
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uint8_t parityCfg[] = { TL16C_NO_PARITY, TL16C_EVEN_PARITY, TL16C_ODD_PARITY }; |
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uint8_t dataCfg[] = { F5BIT_MODE, F6BIT_MODE, F7BIT_MODE, F8BIT_MODE }; |
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uint8_t stopCfg[] = { ONE_STOPBIT, TWO_STOPBITS }; |
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uint8_t regVal = 0; //temp value for reading register and change it's value without clearing it |
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_portD_parity_set = (parity > 0); //Parity set (even or odd) ? |
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//Read register first...
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regVal = readPortD(LCR_REG); |
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//_delay_ms(1);
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setWait(20);
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regVal = DLAB_ERF_EN_BIT; //set LCR[7] = 1 -> enable divisor latch mode
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writePortD(regVal, LCR_REG); //switch Mode (and clear default cfg...)
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//_delay_ms(1);
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setWait(20);
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//Set bus speed (according of 8MHz OSC. -> DL = Fosc/(16*Fbauds*DIV));
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//DIV = 1 or 4 (see TL16C datasheet p.14), we use here DIV = 1
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writePortD(0x00, DLH_REG); //Always 0x00 in our cfg... MAX 12MHz |
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//_delay_ms(1);
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setWait(20);
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//writePortA(busSpeed > 2 ? DL_38400_BAUDS : baudsValues[busSpeed], DLL_REG);
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writePortD(speedCfg[busSpeed], DLL_REG); |
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//_delay_ms(1);
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setWait(20);
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regVal = readPortD(LCR_REG); |
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regVal &= ~(DLAB_ERF_EN_BIT); //set LCR[7] = 0 -> disable divisor latch mode
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//regVal |= dataBits > 3 ? TL16C_WORD_8BITS : wordValues[dataBits]; //set 8bits mode
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//regVal |= (stopBit > 1 ? TL16C_STOPBIT_TWO : stopBitValues[stopBit]) << 2; //set stop bits
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//regVal |= (parity > 2 ? TL16C_PARITY_EVEN : parityValues[parity]) << 3; //set stop bits
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regVal |= dataCfg[dataBits]; //set 8bits mode
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regVal |= stopCfg[stopBit] << 2; //set stop bits |
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regVal |= parityCfg[parity] << 3; //set stop bits |
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writePortD(regVal, LCR_REG); |
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//_delay_ms(1);
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setWait(20);
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writePortD(0x01, FCR_REG); //enable FIFO |
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setWait(20);
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} |
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//////////////////////////////////////////////
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//UART send/reiceive
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void txWriteA(uint8_t b)
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{ |
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writePortA(b, THR_REG); //write to Transmit Holding (that goes into TX FIFO buffer)
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} |
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void txWriteB(uint8_t b)
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{ |
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writePortB(b, THR_REG); //write to Transmit Holding (that goes into TX FIFO buffer)
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} |
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void txWriteC(uint8_t b)
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{ |
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writePortC(b, THR_REG); //write to Transmit Holding (that goes into TX FIFO buffer)
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} |
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void txWriteD(uint8_t b)
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{ |
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writePortD(b, THR_REG); //write to Transmit Holding (that goes into TX FIFO buffer)
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} |
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uint8_t rxReadA(void)
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{ |
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return readPortA(RHR_REG); //read Receive Holding (from RX FIFO buffer) |
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} |
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uint8_t rxReadB(void)
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{ |
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return readPortB(RHR_REG); //read Receive Holding (from RX FIFO buffer) |
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} |
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uint8_t rxReadC(void)
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{ |
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return readPortC(RHR_REG); //read Receive Holding (from RX FIFO buffer) |
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} |
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uint8_t rxReadD(void)
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{ |
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return readPortD(RHR_REG); //read Receive Holding (from RX FIFO buffer) |
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} |
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////////////////////////////////////////
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//RX buf state functions
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bool portA_available()
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{ |
449 |
return (readPortA(LSR_REG) & 0x01); //check if RX FIFO buffer has at least one byte available |
450 |
} |
451 |
|
452 |
|
453 |
bool portB_available()
|
454 |
{ |
455 |
return (readPortB(LSR_REG) & 0x01); //check if RX FIFO buffer has at least one byte available |
456 |
} |
457 |
|
458 |
|
459 |
bool portC_available()
|
460 |
{ |
461 |
return (readPortC(LSR_REG) & 0x01); //check if RX FIFO buffer has at least one byte available |
462 |
} |
463 |
|
464 |
|
465 |
bool portD_available()
|
466 |
{ |
467 |
return (readPortD(LSR_REG) & 0x01); //check if RX FIFO buffer has at least one byte available |
468 |
} |
469 |
|
470 |
|
471 |
///////////////////////////////////////////////////////////////////////
|
472 |
//Parity configuration status
|
473 |
|
474 |
//get status if port has been configured with a parity into the frame
|
475 |
bool getParitySetA()
|
476 |
{ |
477 |
return _portA_parity_set;
|
478 |
} |
479 |
|
480 |
bool getParitySetB()
|
481 |
{ |
482 |
return _portB_parity_set;
|
483 |
} |
484 |
|
485 |
bool getParitySetC()
|
486 |
{ |
487 |
return _portC_parity_set;
|
488 |
} |
489 |
|
490 |
bool getParitySetD()
|
491 |
{ |
492 |
return _portD_parity_set;
|
493 |
} |
494 |
|
495 |
|
496 |
|
497 |
//Get parity/stopbit error status when frame received on port
|
498 |
|
499 |
bool getErrorStatusA()
|
500 |
{ |
501 |
return ((readPortA(LSR_REG) & 0x80) == 0x80); |
502 |
} |
503 |
|
504 |
bool getErrorStatusB()
|
505 |
{ |
506 |
return ((readPortB(LSR_REG) & 0x80) == 0x80); |
507 |
} |
508 |
|
509 |
bool getErrorStatusC()
|
510 |
{ |
511 |
return ((readPortC(LSR_REG) & 0x80) == 0x80); |
512 |
} |
513 |
|
514 |
bool getErrorStatusD()
|
515 |
{ |
516 |
return ((readPortD(LSR_REG) & 0x80) == 0x80); |
517 |
} |
518 |
|
519 |
|
520 |
///////////////////////////////////////////////////////
|
521 |
//write functions
|
522 |
|
523 |
|
524 |
|
525 |
void writePortA(uint8_t reg, uint8_t addr)
|
526 |
{ |
527 |
DATADIR(0xFF); //set I/O on write mode |
528 |
ADDRWRITE(addr); //search uartn register
|
529 |
DATAWRITE(reg); //write data
|
530 |
CLRCSA; //enable uartA call
|
531 |
setWait(3);
|
532 |
CLRWR; //enable write mode
|
533 |
setWait(3);
|
534 |
SETWR; //disable write mode
|
535 |
setWait(3);
|
536 |
SETCSA; //disable uartA call
|
537 |
DATADIR(0x00); //set input mode (to reduce power consumption) |
538 |
} |
539 |
|
540 |
void writePortB(uint8_t reg, uint8_t addr)
|
541 |
{ |
542 |
DATADIR(0xFF); //set I/O on write mode |
543 |
ADDRWRITE(addr); //search uartn register
|
544 |
DATAWRITE(reg); //write data
|
545 |
CLRCSB; //enable uartA call
|
546 |
setWait(3);
|
547 |
CLRWR; //enable write mode
|
548 |
setWait(3);
|
549 |
SETWR; //disable write mode
|
550 |
setWait(3);
|
551 |
SETCSB; //disable uartA call
|
552 |
DATADIR(0x00); //set input mode (to reduce power consumption) |
553 |
} |
554 |
|
555 |
void writePortC(uint8_t reg, uint8_t addr)
|
556 |
{ |
557 |
DATADIR(0xFF); //set I/O on write mode |
558 |
ADDRWRITE(addr); //search uartn register
|
559 |
DATAWRITE(reg); //write data
|
560 |
CLRCSC; //enable uartA call
|
561 |
setWait(3);
|
562 |
CLRWR; //enable write mode
|
563 |
setWait(3);
|
564 |
SETWR; //disable write mode
|
565 |
setWait(3);
|
566 |
SETCSC; //disable uartA call
|
567 |
DATADIR(0x00); //set input mode (to reduce power consumption) |
568 |
} |
569 |
|
570 |
void writePortD(uint8_t reg, uint8_t addr)
|
571 |
{ |
572 |
DATADIR(0xFF); //set I/O on write mode |
573 |
ADDRWRITE(addr); //search uartn register
|
574 |
DATAWRITE(reg); //write data
|
575 |
CLRCSD; //enable uartA call
|
576 |
setWait(3);
|
577 |
CLRWR; //enable write mode
|
578 |
setWait(3);
|
579 |
SETWR; //disable write mode
|
580 |
setWait(3);
|
581 |
SETCSD; //disable uartA call
|
582 |
DATADIR(0x00); //set input mode (to reduce power consumption) |
583 |
} |
584 |
|
585 |
|
586 |
///////////////////////////////////////////////////////
|
587 |
//read functions
|
588 |
|
589 |
|
590 |
uint8_t readPortA(uint8_t addr) |
591 |
{ |
592 |
uint8_t result; |
593 |
DATADIR(0x00); //set I/O on read mode |
594 |
ADDRWRITE(addr); //search uartn register
|
595 |
CLRCSA; //enable uartA call
|
596 |
setWait(3);
|
597 |
CLRRD; //enable read mode
|
598 |
setWait(3);
|
599 |
result = PORTD.IN; //set I/O on read mode
|
600 |
setWait(3);
|
601 |
SETRD; //disable read mode
|
602 |
setWait(3);
|
603 |
SETCSA; //hang up uartA call
|
604 |
return result;
|
605 |
} |
606 |
|
607 |
uint8_t readPortB(uint8_t addr) |
608 |
{ |
609 |
uint8_t result; |
610 |
DATADIR(0x00); //set I/O on read mode |
611 |
ADDRWRITE(addr); //search uartn register
|
612 |
CLRCSB; //enable uartB call
|
613 |
setWait(3);
|
614 |
CLRRD; //enable read mode
|
615 |
setWait(3);
|
616 |
result = PORTD.IN; //set I/O on read mode
|
617 |
setWait(3);
|
618 |
SETRD; //disable read mode
|
619 |
setWait(3);
|
620 |
SETCSB; //hang up uartB call
|
621 |
return result;
|
622 |
} |
623 |
|
624 |
uint8_t readPortC(uint8_t addr) |
625 |
{ |
626 |
uint8_t result; |
627 |
DATADIR(0x00); //set I/O on read mode |
628 |
ADDRWRITE(addr); //search uartn register
|
629 |
CLRCSC; //enable uartC call
|
630 |
setWait(3);
|
631 |
CLRRD; //enable read mode
|
632 |
setWait(3);
|
633 |
result = PORTD.IN; //set I/O on read mode
|
634 |
setWait(3);
|
635 |
SETRD; //disable read mode
|
636 |
setWait(3);
|
637 |
SETCSC; //hang up uartC call
|
638 |
return result;
|
639 |
} |
640 |
|
641 |
uint8_t readPortD(uint8_t addr) |
642 |
{ |
643 |
uint8_t result; |
644 |
DATADIR(0x00); //set I/O on read mode |
645 |
ADDRWRITE(addr); //search uartn register
|
646 |
CLRCSD; //enable uartD call
|
647 |
setWait(3);
|
648 |
CLRRD; //enable read mode
|
649 |
setWait(3);
|
650 |
result = PORTD.IN; //set I/O on read mode
|
651 |
setWait(3);
|
652 |
SETRD; //disable read mode
|
653 |
setWait(3);
|
654 |
SETCSD; //hang up uartD call
|
655 |
return result;
|
656 |
} |
657 |
|
658 |
|
659 |
|
660 |
|
661 |
|
662 |
///////////////////////////////////////////
|
663 |
//Miscellaneous functions
|
664 |
|
665 |
void setWait(uint16_t cnt)
|
666 |
{ |
667 |
uint16_t k = 0;
|
668 |
while(k < cnt)
|
669 |
{ |
670 |
asm("nop"); |
671 |
k++; |
672 |
} |
673 |
} |
674 |
|
675 |
|
676 |
|
677 |
|
678 |
|
679 |
#endif /* XC_HEADER_TEMPLATE_H */ |
680 |
|