root / Version 1.5 / RS232_MUX.X / hardware_TL16C754C.h @ f0dbe1d9
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1 | f0dbe1d9 | Enzo Niro | /* Microchip Technology Inc. and its subsidiaries. You may use this software
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2 | * and any derivatives exclusively with Microchip products.
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3 | *
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4 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER
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5 | * EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED
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6 | * WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A
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7 | * PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP PRODUCTS, COMBINATION
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8 | * WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
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9 | *
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10 | * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
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11 | * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
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12 | * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
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13 | * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE
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14 | * FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS
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15 | * IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF
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16 | * ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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17 | *
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18 | * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE OF THESE
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19 | * TERMS.
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20 | */
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21 | |||
22 | /*
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23 | * File: hardware_TL16C754C.h
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24 | * Author: Enzo Niro
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25 | * Comments: Library for MUX232 to handle TL16C754C chip
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26 | * Revision history: 1.0
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27 | */
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28 | |||
29 | |||
30 | #ifndef RS232_HARDWARETL16_H
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31 | #define RS232_HARDWARETL16_H
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32 | |||
33 | #include <xc.h> // include processor files - each processor file is guarded. |
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34 | |||
35 | |||
36 | |||
37 | |||
38 | //////////////////////////////////////
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39 | //prototypes functions
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40 | |||
41 | |||
42 | //////////////////////////
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43 | //High level functions
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44 | |||
45 | void initPortA(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit);
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46 | void initPortB(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit);
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47 | void initPortC(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit);
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48 | void initPortD(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit);
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49 | |||
50 | //Send bytes throught serial port
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51 | void txWriteA(uint8_t b);
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52 | void txWriteB(uint8_t b);
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53 | void txWriteC(uint8_t b);
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54 | void txWriteD(uint8_t b);
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55 | |||
56 | //Receive bytes from serial port
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57 | uint8_t rxReadA(void);
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58 | uint8_t rxReadB(void);
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59 | uint8_t rxReadC(void);
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60 | uint8_t rxReadD(void);
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61 | |||
62 | //RX buffer control
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63 | |||
64 | //available functions
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65 | bool portA_available();
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66 | bool portB_available();
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67 | bool portC_available();
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68 | bool portD_available();
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69 | |||
70 | //parity functions
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71 | |||
72 | bool getParitySetA();
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73 | bool getParitySetB();
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74 | bool getParitySetC();
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75 | bool getParitySetD();
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76 | |||
77 | /*
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78 |
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79 | TODO : Implement functions...
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80 |
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81 | */
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82 | |||
83 | |||
84 | //////////////////////////
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85 | //Low level functions
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86 | |||
87 | |||
88 | void writePortA(uint8_t reg, uint8_t addr);
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89 | void writePortB(uint8_t reg, uint8_t addr);
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90 | void writePortC(uint8_t reg, uint8_t addr);
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91 | void writePortD(uint8_t reg, uint8_t addr);
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92 | uint8_t readPortA(uint8_t addr); |
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93 | uint8_t readPortB(uint8_t addr); |
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94 | uint8_t readPortC(uint8_t addr); |
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95 | uint8_t readPortD(uint8_t addr); |
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96 | |||
97 | |||
98 | void setWait(uint16_t cnt); //fast delay |
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99 | |||
100 | |||
101 | //////////////////////////////////////////////////////////
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102 | //Values definitions (not supposed to use it directly)
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103 | |||
104 | #define DLAB_ERF_EN_BIT 0x80 |
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105 | |||
106 | |||
107 | #define LCR_REG 0x3 //Static register |
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108 | |||
109 | ///////////////////////////////////////////
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110 | // READ Registers
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111 | |||
112 | #define RHR_REG 0x0 |
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113 | #define IIR_REG 0x2 |
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114 | #define LSR_REG 0x5 |
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115 | #define MSR_REG 0x6 |
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116 | #define FIFORDY_REG 0x7 |
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117 | |||
118 | ///////////////////////////////////////////
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119 | // WRITE Registers
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120 | |||
121 | #define THR_REG 0x0 |
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122 | #define FCR_REG 0x2 |
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123 | |||
124 | ///////////////////////////////////////////
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125 | // READ/WRITE Registers
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126 | |||
127 | #define IER_REG 0x1 |
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128 | #define LCR_REG 0x3 |
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129 | #define MCR_REG 0x4 |
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130 | #define SPR_REG 0x7 |
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131 | #define DLL_REG 0x0 |
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132 | #define DLH_REG 0x1 |
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133 | #define EFR_REG 0x2 |
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134 | #define XON1_REG 0x4 |
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135 | #define XON2_REG 0x5 |
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136 | #define XOFF1_REG 0x6 |
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137 | #define XOFF2_REG 0x7 |
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138 | #define TCR_REG 0x6 |
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139 | #define TLR_REG 0x7 |
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140 | |||
141 | |||
142 | |||
143 | |||
144 | ///////////////////////////////////////////////////////
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145 | //CTRL, ADDR and DATA buses
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146 | |||
147 | //Data pins
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148 | #define DATAWRITE(x) PORTD.OUT = x
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149 | #define DATADIR(x) PORTD.DIR = x
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150 | #define DATAREAD PORTD.IN
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151 | |||
152 | //Address pins
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153 | #define ADDRWRITE(x) PORTE.OUT = x
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154 | #define ADDR_ENABLE PORTE.DIR |= 0x07 |
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155 | |||
156 | |||
157 | //Controls pins
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158 | #define ENABLE_POW_SUPPLY_PIN PORTF.DIR |= 0x01 |
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159 | #define ENABLE_WR_RD_PINS PORTB.DIR |= 0x30 |
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160 | #define ENABLE_CS_PINS PORTB.DIR |= 0x0F |
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161 | #define ENABLE_RESET_PIN PORTE.DIR |= 0x08 |
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162 | #define POWER_ON PORTF.OUT |= 0x01 |
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163 | #define POWER_OFF PORTF.OUT &= ~(0x01) |
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164 | #define SETRST PORTE.OUT |= 0x08 |
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165 | #define SETWR PORTB.OUT |= 0x10 |
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166 | #define SETRD PORTB.OUT |= 0x20 |
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167 | #define SETCSA PORTB.OUT |= 0x01 |
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168 | #define SETCSB PORTB.OUT |= 0x02 |
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169 | #define SETCSC PORTB.OUT |= 0x04 |
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170 | #define SETCSD PORTB.OUT |= 0x08 |
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171 | #define CLRRST PORTE.OUT &= ~(0x08) |
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172 | #define CLRWR PORTB.OUT &= ~(0x10) |
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173 | #define CLRRD PORTB.OUT &= ~(0x20) |
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174 | #define CLRCSA PORTB.OUT &= ~(0x01) |
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175 | #define CLRCSB PORTB.OUT &= ~(0x02) |
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176 | #define CLRCSC PORTB.OUT &= ~(0x04) |
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177 | #define CLRCSD PORTB.OUT &= ~(0x08) |
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178 | |||
179 | |||
180 | ///////////////////////////////////////////////////////////////////////////////
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181 | //Private vars
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182 | |||
183 | bool _portA_parity_set;
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184 | bool _portB_parity_set;
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185 | bool _portC_parity_set;
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186 | bool _portD_parity_set;
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187 | |||
188 | |||
189 | |||
190 | ///////////////////////////////////////////////////////////////////////////////
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191 | //Functions
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192 | |||
193 | //////////////////////////////////////
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194 | //High level functions
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195 | |||
196 | void initPortA(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit)
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197 | { |
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198 | |||
199 | uint8_t regVal = 0; //temp value for reading register and change it's value without clearing it |
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200 | |||
201 | _portA_parity_set = (parity > 0); //Parity set (even or odd) ? |
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202 | |||
203 | |||
204 | //Read register first...
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205 | regVal = readPortA(LCR_REG); |
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206 | //_delay_ms(1);
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207 | setWait(20);
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208 | regVal = DLAB_ERF_EN_BIT; //set LCR[7] = 1 -> enable divisor latch mode
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209 | writePortA(regVal, LCR_REG); //switch Mode
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210 | //_delay_ms(1);
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211 | setWait(20);
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212 | //Set bus speed (according of 8MHz OSC. -> DL = Fosc/(16*Fbauds*DIV));
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213 | //DIV = 1 or 4 (see TL16C datasheet p.14), we use here DIV = 1
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214 | writePortA(0x00, DLH_REG); //Always 0x00 in our cfg... MAX 12MHz |
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215 | //_delay_ms(1);
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216 | setWait(20);
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217 | //writePortA(busSpeed > 2 ? DL_38400_BAUDS : baudsValues[busSpeed], DLL_REG);
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218 | writePortA(busSpeed, DLL_REG); |
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219 | //_delay_ms(1);
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220 | setWait(20);
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221 | |||
222 | regVal = readPortA(LCR_REG); |
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223 | regVal &= ~(DLAB_ERF_EN_BIT); //set LCR[7] = 0 -> disable divisor latch mode
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224 | |||
225 | //regVal |= dataBits > 3 ? TL16C_WORD_8BITS : wordValues[dataBits]; //set 8bits mode
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226 | //regVal |= (stopBit > 1 ? TL16C_STOPBIT_TWO : stopBitValues[stopBit]) << 2; //set stop bits
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227 | //regVal |= (parity > 2 ? TL16C_PARITY_EVEN : parityValues[parity]) << 3; //set stop bits
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228 | regVal |= dataBits; //set 8bits mode
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229 | regVal |= stopBit << 2; //set stop bits |
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230 | regVal |= parity << 3; //set stop bits |
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231 | writePortA(regVal, LCR_REG); |
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232 | //_delay_ms(1);
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233 | setWait(20);
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234 | writePortA(0x01, FCR_REG); //enable FIFO |
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235 | setWait(20);
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236 | } |
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237 | |||
238 | |||
239 | void initPortB(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit)
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240 | { |
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241 | |||
242 | uint8_t regVal = 0; //temp value for reading register and change it's value without clearing it |
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243 | |||
244 | _portB_parity_set = (parity > 0); //Parity set (even or odd) ? |
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245 | |||
246 | |||
247 | //Read register first...
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248 | regVal = readPortB(LCR_REG); |
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249 | //_delay_ms(1);
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250 | setWait(20);
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251 | regVal = DLAB_ERF_EN_BIT; //set LCR[7] = 1 -> enable divisor latch mode
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252 | writePortB(regVal, LCR_REG); //switch Mode
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253 | //_delay_ms(1);
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254 | setWait(20);
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255 | //Set bus speed (according of 8MHz OSC. -> DL = Fosc/(16*Fbauds*DIV));
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256 | //DIV = 1 or 4 (see TL16C datasheet p.14), we use here DIV = 1
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257 | writePortB(0x00, DLH_REG); //Always 0x00 in our cfg... MAX 12MHz |
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258 | //_delay_ms(1);
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259 | setWait(20);
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260 | //writePortA(busSpeed > 2 ? DL_38400_BAUDS : baudsValues[busSpeed], DLL_REG);
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261 | writePortB(busSpeed, DLL_REG); |
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262 | //_delay_ms(1);
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263 | setWait(20);
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264 | |||
265 | regVal = readPortB(LCR_REG); |
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266 | regVal &= ~(DLAB_ERF_EN_BIT); //set LCR[7] = 0 -> disable divisor latch mode
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267 | |||
268 | //regVal |= dataBits > 3 ? TL16C_WORD_8BITS : wordValues[dataBits]; //set 8bits mode
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269 | //regVal |= (stopBit > 1 ? TL16C_STOPBIT_TWO : stopBitValues[stopBit]) << 2; //set stop bits
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270 | //regVal |= (parity > 2 ? TL16C_PARITY_EVEN : parityValues[parity]) << 3; //set stop bits
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271 | regVal |= dataBits; //set 8bits mode
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272 | regVal |= stopBit << 2; //set stop bits |
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273 | regVal |= parity << 3; //set stop bits |
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274 | writePortB(regVal, LCR_REG); |
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275 | //_delay_ms(1);
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276 | setWait(20);
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277 | writePortB(0x01, FCR_REG); //enable FIFO |
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278 | setWait(20);
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279 | } |
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280 | |||
281 | |||
282 | void initPortC(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit)
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283 | { |
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284 | uint8_t regVal = 0; //temp value for reading register and change it's value without clearing it |
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285 | |||
286 | _portC_parity_set = (parity > 0); //Parity set (even or odd) ? |
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287 | |||
288 | |||
289 | //Read register first...
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290 | regVal = readPortC(LCR_REG); |
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291 | //_delay_ms(1);
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292 | setWait(20);
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293 | regVal = DLAB_ERF_EN_BIT; //set LCR[7] = 1 -> enable divisor latch mode
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294 | writePortC(regVal, LCR_REG); //switch Mode
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295 | //_delay_ms(1);
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296 | setWait(20);
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297 | //Set bus speed (according of 8MHz OSC. -> DL = Fosc/(16*Fbauds*DIV));
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298 | //DIV = 1 or 4 (see TL16C datasheet p.14), we use here DIV = 1
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299 | writePortC(0x00, DLH_REG); //Always 0x00 in our cfg... MAX 12MHz |
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300 | //_delay_ms(1);
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301 | setWait(20);
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302 | //writePortA(busSpeed > 2 ? DL_38400_BAUDS : baudsValues[busSpeed], DLL_REG);
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303 | writePortC(busSpeed, DLL_REG); |
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304 | //_delay_ms(1);
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305 | setWait(20);
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306 | |||
307 | regVal = readPortC(LCR_REG); |
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308 | regVal &= ~(DLAB_ERF_EN_BIT); //set LCR[7] = 0 -> disable divisor latch mode
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309 | |||
310 | //regVal |= dataBits > 3 ? TL16C_WORD_8BITS : wordValues[dataBits]; //set 8bits mode
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311 | //regVal |= (stopBit > 1 ? TL16C_STOPBIT_TWO : stopBitValues[stopBit]) << 2; //set stop bits
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312 | //regVal |= (parity > 2 ? TL16C_PARITY_EVEN : parityValues[parity]) << 3; //set stop bits
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313 | regVal |= dataBits; //set 8bits mode
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314 | regVal |= stopBit << 2; //set stop bits |
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315 | regVal |= parity << 3; //set stop bits |
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316 | writePortC(regVal, LCR_REG); |
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317 | //_delay_ms(1);
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318 | setWait(20);
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319 | writePortC(0x01, FCR_REG); //enable FIFO |
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320 | setWait(20);
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321 | } |
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322 | |||
323 | |||
324 | |||
325 | void initPortD(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit)
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326 | { |
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327 | uint8_t regVal = 0; //temp value for reading register and change it's value without clearing it |
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328 | |||
329 | _portD_parity_set = (parity > 0); //Parity set (even or odd) ? |
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330 | |||
331 | |||
332 | //Read register first...
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333 | regVal = readPortD(LCR_REG); |
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334 | //_delay_ms(1);
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335 | setWait(20);
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336 | regVal = DLAB_ERF_EN_BIT; //set LCR[7] = 1 -> enable divisor latch mode
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337 | writePortD(regVal, LCR_REG); //switch Mode (and clear default cfg...)
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338 | //_delay_ms(1);
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339 | setWait(20);
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340 | //Set bus speed (according of 8MHz OSC. -> DL = Fosc/(16*Fbauds*DIV));
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341 | //DIV = 1 or 4 (see TL16C datasheet p.14), we use here DIV = 1
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342 | writePortD(0x00, DLH_REG); //Always 0x00 in our cfg... MAX 12MHz |
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343 | //_delay_ms(1);
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344 | setWait(20);
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345 | //writePortA(busSpeed > 2 ? DL_38400_BAUDS : baudsValues[busSpeed], DLL_REG);
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346 | writePortD(busSpeed, DLL_REG); |
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347 | //_delay_ms(1);
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348 | setWait(20);
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349 | |||
350 | regVal = readPortD(LCR_REG); |
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351 | regVal &= ~(DLAB_ERF_EN_BIT); //set LCR[7] = 0 -> disable divisor latch mode
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352 | |||
353 | //regVal |= dataBits > 3 ? TL16C_WORD_8BITS : wordValues[dataBits]; //set 8bits mode
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354 | //regVal |= (stopBit > 1 ? TL16C_STOPBIT_TWO : stopBitValues[stopBit]) << 2; //set stop bits
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355 | //regVal |= (parity > 2 ? TL16C_PARITY_EVEN : parityValues[parity]) << 3; //set stop bits
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356 | regVal |= dataBits; //set 8bits mode
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357 | regVal |= stopBit << 2; //set stop bits |
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358 | regVal |= parity << 3; //set stop bits |
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359 | writePortD(regVal, LCR_REG); |
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360 | //_delay_ms(1);
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361 | setWait(20);
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362 | writePortD(0x01, FCR_REG); //enable FIFO |
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363 | setWait(20);
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364 | } |
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365 | |||
366 | |||
367 | |||
368 | //////////////////////////////////////////////
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369 | //UART send/reiceive
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370 | |||
371 | void txWriteA(uint8_t b)
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372 | { |
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373 | writePortA(b, THR_REG); //write to Transmit Holding (that goes into TX FIFO buffer)
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374 | } |
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375 | |||
376 | |||
377 | void txWriteB(uint8_t b)
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378 | { |
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379 | writePortB(b, THR_REG); //write to Transmit Holding (that goes into TX FIFO buffer)
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380 | } |
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381 | |||
382 | |||
383 | void txWriteC(uint8_t b)
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384 | { |
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385 | writePortC(b, THR_REG); //write to Transmit Holding (that goes into TX FIFO buffer)
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386 | } |
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387 | |||
388 | |||
389 | void txWriteD(uint8_t b)
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390 | { |
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391 | writePortD(b, THR_REG); //write to Transmit Holding (that goes into TX FIFO buffer)
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392 | } |
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393 | |||
394 | |||
395 | |||
396 | uint8_t rxReadA(void)
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397 | { |
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398 | return readPortA(RHR_REG); //read Receive Holding (from RX FIFO buffer) |
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399 | } |
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400 | |||
401 | |||
402 | uint8_t rxReadB(void)
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403 | { |
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404 | return readPortB(RHR_REG); //read Receive Holding (from RX FIFO buffer) |
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405 | } |
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406 | |||
407 | |||
408 | uint8_t rxReadC(void)
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409 | { |
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410 | return readPortC(RHR_REG); //read Receive Holding (from RX FIFO buffer) |
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411 | } |
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412 | |||
413 | |||
414 | uint8_t rxReadD(void)
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415 | { |
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416 | return readPortD(RHR_REG); //read Receive Holding (from RX FIFO buffer) |
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417 | } |
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418 | |||
419 | |||
420 | ////////////////////////////////////////
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421 | //RX buf state functions
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422 | |||
423 | bool portA_available()
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424 | { |
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425 | return (readPortA(LSR_REG) & 0x01); //check if RX FIFO buffer has at least one byte available |
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426 | } |
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427 | |||
428 | |||
429 | bool portB_available()
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430 | { |
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431 | return (readPortB(LSR_REG) & 0x01); //check if RX FIFO buffer has at least one byte available |
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432 | } |
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433 | |||
434 | |||
435 | bool portC_available()
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436 | { |
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437 | return (readPortC(LSR_REG) & 0x01); //check if RX FIFO buffer has at least one byte available |
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438 | } |
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439 | |||
440 | |||
441 | bool portD_available()
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442 | { |
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443 | return (readPortD(LSR_REG) & 0x01); //check if RX FIFO buffer has at least one byte available |
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444 | } |
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445 | |||
446 | |||
447 | ///////////////////////////////////////////////////////////////////////
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448 | //Parity configuration status
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449 | |||
450 | //get status if port has been configured with a parity into the frame
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451 | bool getParitySetA()
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452 | { |
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453 | return _portA_parity_set;
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454 | } |
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455 | |||
456 | bool getParitySetB()
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457 | { |
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458 | return _portB_parity_set;
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459 | } |
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460 | |||
461 | bool getParitySetC()
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462 | { |
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463 | return _portC_parity_set;
|
||
464 | } |
||
465 | |||
466 | bool getParitySetD()
|
||
467 | { |
||
468 | return _portD_parity_set;
|
||
469 | } |
||
470 | |||
471 | |||
472 | |||
473 | //Get parity/stopbit error status when frame received on port
|
||
474 | |||
475 | bool getErrorStatusA()
|
||
476 | { |
||
477 | return ((readPortA(LSR_REG) & 0x80) == 0x80); |
||
478 | } |
||
479 | |||
480 | bool getErrorStatusB()
|
||
481 | { |
||
482 | return ((readPortB(LSR_REG) & 0x80) == 0x80); |
||
483 | } |
||
484 | |||
485 | bool getErrorStatusC()
|
||
486 | { |
||
487 | return ((readPortC(LSR_REG) & 0x80) == 0x80); |
||
488 | } |
||
489 | |||
490 | bool getErrorStatusD()
|
||
491 | { |
||
492 | return ((readPortD(LSR_REG) & 0x80) == 0x80); |
||
493 | } |
||
494 | |||
495 | |||
496 | ///////////////////////////////////////////////////////
|
||
497 | //write functions
|
||
498 | |||
499 | |||
500 | |||
501 | void writePortA(uint8_t reg, uint8_t addr)
|
||
502 | { |
||
503 | DATADIR(0xFF); //set I/O on write mode |
||
504 | ADDRWRITE(addr); //search uartn register
|
||
505 | DATAWRITE(reg); //write data
|
||
506 | CLRCSA; //enable uartA call
|
||
507 | setWait(3);
|
||
508 | CLRWR; //enable write mode
|
||
509 | setWait(3);
|
||
510 | SETWR; //disable write mode
|
||
511 | setWait(3);
|
||
512 | SETCSA; //disable uartA call
|
||
513 | DATADIR(0x00); //set input mode (to reduce power consumption) |
||
514 | } |
||
515 | |||
516 | void writePortB(uint8_t reg, uint8_t addr)
|
||
517 | { |
||
518 | DATADIR(0xFF); //set I/O on write mode |
||
519 | ADDRWRITE(addr); //search uartn register
|
||
520 | DATAWRITE(reg); //write data
|
||
521 | CLRCSB; //enable uartA call
|
||
522 | setWait(3);
|
||
523 | CLRWR; //enable write mode
|
||
524 | setWait(3);
|
||
525 | SETWR; //disable write mode
|
||
526 | setWait(3);
|
||
527 | SETCSB; //disable uartA call
|
||
528 | DATADIR(0x00); //set input mode (to reduce power consumption) |
||
529 | } |
||
530 | |||
531 | void writePortC(uint8_t reg, uint8_t addr)
|
||
532 | { |
||
533 | DATADIR(0xFF); //set I/O on write mode |
||
534 | ADDRWRITE(addr); //search uartn register
|
||
535 | DATAWRITE(reg); //write data
|
||
536 | CLRCSC; //enable uartA call
|
||
537 | setWait(3);
|
||
538 | CLRWR; //enable write mode
|
||
539 | setWait(3);
|
||
540 | SETWR; //disable write mode
|
||
541 | setWait(3);
|
||
542 | SETCSC; //disable uartA call
|
||
543 | DATADIR(0x00); //set input mode (to reduce power consumption) |
||
544 | } |
||
545 | |||
546 | void writePortD(uint8_t reg, uint8_t addr)
|
||
547 | { |
||
548 | DATADIR(0xFF); //set I/O on write mode |
||
549 | ADDRWRITE(addr); //search uartn register
|
||
550 | DATAWRITE(reg); //write data
|
||
551 | CLRCSD; //enable uartA call
|
||
552 | setWait(3);
|
||
553 | CLRWR; //enable write mode
|
||
554 | setWait(3);
|
||
555 | SETWR; //disable write mode
|
||
556 | setWait(3);
|
||
557 | SETCSD; //disable uartA call
|
||
558 | DATADIR(0x00); //set input mode (to reduce power consumption) |
||
559 | } |
||
560 | |||
561 | |||
562 | ///////////////////////////////////////////////////////
|
||
563 | //read functions
|
||
564 | |||
565 | |||
566 | uint8_t readPortA(uint8_t addr) |
||
567 | { |
||
568 | uint8_t result; |
||
569 | DATADIR(0x00); //set I/O on read mode |
||
570 | ADDRWRITE(addr); //search uartn register
|
||
571 | CLRCSA; //enable uartA call
|
||
572 | setWait(3);
|
||
573 | CLRRD; //enable read mode
|
||
574 | setWait(3);
|
||
575 | result = PORTD.IN; //set I/O on read mode
|
||
576 | setWait(3);
|
||
577 | SETRD; //disable read mode
|
||
578 | setWait(3);
|
||
579 | SETCSA; //hang up uartA call
|
||
580 | return result;
|
||
581 | } |
||
582 | |||
583 | uint8_t readPortB(uint8_t addr) |
||
584 | { |
||
585 | uint8_t result; |
||
586 | DATADIR(0x00); //set I/O on read mode |
||
587 | ADDRWRITE(addr); //search uartn register
|
||
588 | CLRCSB; //enable uartB call
|
||
589 | setWait(3);
|
||
590 | CLRRD; //enable read mode
|
||
591 | setWait(3);
|
||
592 | result = PORTD.IN; //set I/O on read mode
|
||
593 | setWait(3);
|
||
594 | SETRD; //disable read mode
|
||
595 | setWait(3);
|
||
596 | SETCSB; //hang up uartB call
|
||
597 | return result;
|
||
598 | } |
||
599 | |||
600 | uint8_t readPortC(uint8_t addr) |
||
601 | { |
||
602 | uint8_t result; |
||
603 | DATADIR(0x00); //set I/O on read mode |
||
604 | ADDRWRITE(addr); //search uartn register
|
||
605 | CLRCSC; //enable uartC call
|
||
606 | setWait(3);
|
||
607 | CLRRD; //enable read mode
|
||
608 | setWait(3);
|
||
609 | result = PORTD.IN; //set I/O on read mode
|
||
610 | setWait(3);
|
||
611 | SETRD; //disable read mode
|
||
612 | setWait(3);
|
||
613 | SETCSC; //hang up uartC call
|
||
614 | return result;
|
||
615 | } |
||
616 | |||
617 | uint8_t readPortD(uint8_t addr) |
||
618 | { |
||
619 | uint8_t result; |
||
620 | DATADIR(0x00); //set I/O on read mode |
||
621 | ADDRWRITE(addr); //search uartn register
|
||
622 | CLRCSD; //enable uartD call
|
||
623 | setWait(3);
|
||
624 | CLRRD; //enable read mode
|
||
625 | setWait(3);
|
||
626 | result = PORTD.IN; //set I/O on read mode
|
||
627 | setWait(3);
|
||
628 | SETRD; //disable read mode
|
||
629 | setWait(3);
|
||
630 | SETCSD; //hang up uartD call
|
||
631 | return result;
|
||
632 | } |
||
633 | |||
634 | |||
635 | |||
636 | |||
637 | |||
638 | ///////////////////////////////////////////
|
||
639 | //Miscellaneous functions
|
||
640 | |||
641 | void setWait(uint16_t cnt)
|
||
642 | { |
||
643 | uint16_t k = 0;
|
||
644 | while(k < cnt)
|
||
645 | { |
||
646 | asm("nop"); |
||
647 | k++; |
||
648 | } |
||
649 | } |
||
650 | |||
651 | |||
652 | |||
653 | |||
654 | |||
655 | #endif /* XC_HEADER_TEMPLATE_H */ |