Statistiques
| Branche: | Révision:

root / Version 1.5 / RS232_MUX.X / hardware_TL16C754C.h @ f0dbe1d9

Historique | Voir | Annoter | Télécharger (17,468 ko)

1
/* Microchip Technology Inc. and its subsidiaries.  You may use this software 
2
 * and any derivatives exclusively with Microchip products. 
3
 * 
4
 * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS".  NO WARRANTIES, WHETHER 
5
 * EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED 
6
 * WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A 
7
 * PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP PRODUCTS, COMBINATION 
8
 * WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. 
9
 *
10
 * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, 
11
 * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND 
12
 * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS 
13
 * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE 
14
 * FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS 
15
 * IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF 
16
 * ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
17
 *
18
 * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE OF THESE 
19
 * TERMS. 
20
 */
21

    
22
/* 
23
 * File: hardware_TL16C754C.h  
24
 * Author: Enzo Niro
25
 * Comments: Library for MUX232 to handle TL16C754C chip
26
 * Revision history: 1.0
27
 */
28

    
29

    
30
#ifndef RS232_HARDWARETL16_H
31
#define        RS232_HARDWARETL16_H
32

    
33
#include <xc.h> // include processor files - each processor file is guarded. 
34

    
35

    
36

    
37

    
38
//////////////////////////////////////
39
//prototypes functions
40

    
41

    
42
//////////////////////////
43
//High level functions
44

    
45
void initPortA(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit);
46
void initPortB(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit);
47
void initPortC(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit);
48
void initPortD(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit);
49

    
50
//Send bytes throught serial port
51
void txWriteA(uint8_t b);
52
void txWriteB(uint8_t b);
53
void txWriteC(uint8_t b);
54
void txWriteD(uint8_t b);
55

    
56
//Receive bytes from serial port
57
uint8_t rxReadA(void);
58
uint8_t rxReadB(void);
59
uint8_t rxReadC(void);
60
uint8_t rxReadD(void);
61

    
62
//RX buffer control
63

    
64
//available functions
65
bool portA_available();
66
bool portB_available();
67
bool portC_available();
68
bool portD_available();
69

    
70
//parity functions
71

    
72
bool getParitySetA();
73
bool getParitySetB();
74
bool getParitySetC();
75
bool getParitySetD();
76

    
77
/*
78
 
79
 TODO : Implement functions...
80
 
81
 */
82

    
83

    
84
//////////////////////////
85
//Low level functions
86

    
87

    
88
void writePortA(uint8_t reg, uint8_t addr);
89
void writePortB(uint8_t reg, uint8_t addr);
90
void writePortC(uint8_t reg, uint8_t addr);
91
void writePortD(uint8_t reg, uint8_t addr);
92
uint8_t readPortA(uint8_t addr);
93
uint8_t readPortB(uint8_t addr);
94
uint8_t readPortC(uint8_t addr);
95
uint8_t readPortD(uint8_t addr);
96

    
97

    
98
void setWait(uint16_t cnt); //fast delay
99

    
100

    
101
//////////////////////////////////////////////////////////
102
//Values definitions (not supposed to use it directly)
103

    
104
#define DLAB_ERF_EN_BIT     0x80
105

    
106

    
107
#define LCR_REG             0x3 //Static register
108

    
109
///////////////////////////////////////////
110
// READ Registers
111

    
112
#define RHR_REG         0x0
113
#define IIR_REG         0x2
114
#define LSR_REG         0x5
115
#define MSR_REG         0x6
116
#define FIFORDY_REG     0x7
117

    
118
///////////////////////////////////////////
119
// WRITE Registers
120

    
121
#define THR_REG     0x0
122
#define FCR_REG     0x2
123

    
124
///////////////////////////////////////////
125
// READ/WRITE Registers
126

    
127
#define IER_REG         0x1
128
#define LCR_REG         0x3
129
#define MCR_REG         0x4
130
#define SPR_REG         0x7
131
#define DLL_REG         0x0
132
#define DLH_REG         0x1
133
#define EFR_REG         0x2
134
#define XON1_REG        0x4
135
#define XON2_REG        0x5
136
#define XOFF1_REG       0x6
137
#define XOFF2_REG       0x7
138
#define TCR_REG         0x6
139
#define TLR_REG         0x7
140

    
141

    
142

    
143

    
144
///////////////////////////////////////////////////////
145
//CTRL, ADDR and DATA buses
146

    
147
//Data pins
148
#define DATAWRITE(x)        PORTD.OUT = x
149
#define DATADIR(x)          PORTD.DIR = x
150
#define DATAREAD            PORTD.IN
151

    
152
//Address pins
153
#define ADDRWRITE(x)        PORTE.OUT = x
154
#define ADDR_ENABLE         PORTE.DIR |= 0x07
155

    
156

    
157
//Controls pins
158
#define ENABLE_POW_SUPPLY_PIN   PORTF.DIR |= 0x01
159
#define ENABLE_WR_RD_PINS       PORTB.DIR |= 0x30
160
#define ENABLE_CS_PINS          PORTB.DIR |= 0x0F
161
#define ENABLE_RESET_PIN        PORTE.DIR |= 0x08
162
#define POWER_ON                PORTF.OUT |= 0x01
163
#define POWER_OFF               PORTF.OUT &= ~(0x01)
164
#define SETRST                  PORTE.OUT |= 0x08
165
#define SETWR                   PORTB.OUT |= 0x10
166
#define SETRD                   PORTB.OUT |= 0x20
167
#define SETCSA                  PORTB.OUT |= 0x01
168
#define SETCSB                  PORTB.OUT |= 0x02
169
#define SETCSC                  PORTB.OUT |= 0x04
170
#define SETCSD                  PORTB.OUT |= 0x08
171
#define CLRRST                  PORTE.OUT &= ~(0x08)
172
#define CLRWR                   PORTB.OUT &= ~(0x10)
173
#define CLRRD                   PORTB.OUT &= ~(0x20)
174
#define CLRCSA                  PORTB.OUT &= ~(0x01)
175
#define CLRCSB                  PORTB.OUT &= ~(0x02)
176
#define CLRCSC                  PORTB.OUT &= ~(0x04)
177
#define CLRCSD                  PORTB.OUT &= ~(0x08)
178

    
179

    
180
///////////////////////////////////////////////////////////////////////////////
181
//Private vars
182

    
183
bool _portA_parity_set;
184
bool _portB_parity_set;
185
bool _portC_parity_set;
186
bool _portD_parity_set;
187

    
188

    
189

    
190
///////////////////////////////////////////////////////////////////////////////
191
//Functions
192

    
193
//////////////////////////////////////
194
//High level functions
195

    
196
void initPortA(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit)
197
{
198
    
199
    uint8_t regVal = 0; //temp value for reading register and change it's value without clearing it
200
    
201
    _portA_parity_set = (parity > 0); //Parity set (even or odd) ?
202
    
203
    
204
    //Read register first...
205
    regVal = readPortA(LCR_REG);
206
    //_delay_ms(1);
207
    setWait(20);
208
    regVal = DLAB_ERF_EN_BIT; //set LCR[7] = 1 -> enable divisor latch mode
209
    writePortA(regVal, LCR_REG); //switch Mode
210
    //_delay_ms(1);
211
    setWait(20);
212
    //Set bus speed (according of 8MHz OSC. -> DL = Fosc/(16*Fbauds*DIV)); 
213
    //DIV = 1 or 4 (see TL16C datasheet p.14), we use here DIV = 1 
214
    writePortA(0x00, DLH_REG); //Always 0x00 in our cfg... MAX 12MHz
215
    //_delay_ms(1);
216
    setWait(20);
217
    //writePortA(busSpeed > 2 ? DL_38400_BAUDS : baudsValues[busSpeed], DLL_REG);
218
    writePortA(busSpeed, DLL_REG);
219
    //_delay_ms(1);
220
    setWait(20);
221
    
222
    regVal = readPortA(LCR_REG);
223
    regVal &= ~(DLAB_ERF_EN_BIT); //set LCR[7] = 0 -> disable divisor latch mode
224
    
225
    //regVal |= dataBits > 3 ? TL16C_WORD_8BITS : wordValues[dataBits]; //set 8bits mode
226
    //regVal |= (stopBit > 1 ? TL16C_STOPBIT_TWO : stopBitValues[stopBit]) << 2; //set stop bits
227
    //regVal |= (parity > 2 ? TL16C_PARITY_EVEN : parityValues[parity]) << 3; //set stop bits
228
    regVal |= dataBits; //set 8bits mode
229
    regVal |= stopBit << 2; //set stop bits
230
    regVal |= parity << 3; //set stop bits
231
    writePortA(regVal, LCR_REG);
232
    //_delay_ms(1);
233
    setWait(20);
234
    writePortA(0x01, FCR_REG); //enable FIFO
235
    setWait(20);
236
}
237

    
238

    
239
void initPortB(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit)
240
{
241
    
242
    uint8_t regVal = 0; //temp value for reading register and change it's value without clearing it
243
    
244
    _portB_parity_set = (parity > 0); //Parity set (even or odd) ?
245
    
246
    
247
    //Read register first...
248
    regVal = readPortB(LCR_REG);
249
    //_delay_ms(1);
250
    setWait(20);
251
    regVal = DLAB_ERF_EN_BIT; //set LCR[7] = 1 -> enable divisor latch mode
252
    writePortB(regVal, LCR_REG); //switch Mode
253
    //_delay_ms(1);
254
    setWait(20);
255
    //Set bus speed (according of 8MHz OSC. -> DL = Fosc/(16*Fbauds*DIV)); 
256
    //DIV = 1 or 4 (see TL16C datasheet p.14), we use here DIV = 1 
257
    writePortB(0x00, DLH_REG); //Always 0x00 in our cfg... MAX 12MHz
258
    //_delay_ms(1);
259
    setWait(20);
260
    //writePortA(busSpeed > 2 ? DL_38400_BAUDS : baudsValues[busSpeed], DLL_REG);
261
    writePortB(busSpeed, DLL_REG);
262
    //_delay_ms(1);
263
    setWait(20);
264
    
265
    regVal = readPortB(LCR_REG);
266
    regVal &= ~(DLAB_ERF_EN_BIT); //set LCR[7] = 0 -> disable divisor latch mode
267
    
268
    //regVal |= dataBits > 3 ? TL16C_WORD_8BITS : wordValues[dataBits]; //set 8bits mode
269
    //regVal |= (stopBit > 1 ? TL16C_STOPBIT_TWO : stopBitValues[stopBit]) << 2; //set stop bits
270
    //regVal |= (parity > 2 ? TL16C_PARITY_EVEN : parityValues[parity]) << 3; //set stop bits
271
    regVal |= dataBits; //set 8bits mode
272
    regVal |= stopBit << 2; //set stop bits
273
    regVal |= parity << 3; //set stop bits
274
    writePortB(regVal, LCR_REG);
275
    //_delay_ms(1);
276
    setWait(20);
277
    writePortB(0x01, FCR_REG); //enable FIFO
278
    setWait(20);
279
}
280

    
281

    
282
void initPortC(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit)
283
{
284
    uint8_t regVal = 0; //temp value for reading register and change it's value without clearing it
285
    
286
    _portC_parity_set = (parity > 0); //Parity set (even or odd) ?
287
    
288
    
289
    //Read register first...
290
    regVal = readPortC(LCR_REG);
291
    //_delay_ms(1);
292
    setWait(20);
293
    regVal = DLAB_ERF_EN_BIT; //set LCR[7] = 1 -> enable divisor latch mode
294
    writePortC(regVal, LCR_REG); //switch Mode
295
    //_delay_ms(1);
296
    setWait(20);
297
    //Set bus speed (according of 8MHz OSC. -> DL = Fosc/(16*Fbauds*DIV)); 
298
    //DIV = 1 or 4 (see TL16C datasheet p.14), we use here DIV = 1 
299
    writePortC(0x00, DLH_REG); //Always 0x00 in our cfg... MAX 12MHz
300
    //_delay_ms(1);
301
    setWait(20);
302
    //writePortA(busSpeed > 2 ? DL_38400_BAUDS : baudsValues[busSpeed], DLL_REG);
303
    writePortC(busSpeed, DLL_REG);
304
    //_delay_ms(1);
305
    setWait(20);
306
    
307
    regVal = readPortC(LCR_REG);
308
    regVal &= ~(DLAB_ERF_EN_BIT); //set LCR[7] = 0 -> disable divisor latch mode
309
    
310
    //regVal |= dataBits > 3 ? TL16C_WORD_8BITS : wordValues[dataBits]; //set 8bits mode
311
    //regVal |= (stopBit > 1 ? TL16C_STOPBIT_TWO : stopBitValues[stopBit]) << 2; //set stop bits
312
    //regVal |= (parity > 2 ? TL16C_PARITY_EVEN : parityValues[parity]) << 3; //set stop bits
313
    regVal |= dataBits; //set 8bits mode
314
    regVal |= stopBit << 2; //set stop bits
315
    regVal |= parity << 3; //set stop bits
316
    writePortC(regVal, LCR_REG);
317
    //_delay_ms(1);
318
    setWait(20);
319
    writePortC(0x01, FCR_REG); //enable FIFO
320
    setWait(20);
321
}
322

    
323

    
324

    
325
void initPortD(uint8_t busSpeed, uint8_t dataBits, uint8_t parity, uint8_t stopBit)
326
{
327
    uint8_t regVal = 0; //temp value for reading register and change it's value without clearing it
328
    
329
    _portD_parity_set = (parity > 0); //Parity set (even or odd) ?
330
    
331
    
332
    //Read register first...
333
    regVal = readPortD(LCR_REG);
334
    //_delay_ms(1);
335
    setWait(20);
336
    regVal = DLAB_ERF_EN_BIT; //set LCR[7] = 1 -> enable divisor latch mode
337
    writePortD(regVal, LCR_REG); //switch Mode (and clear default cfg...)
338
    //_delay_ms(1);
339
    setWait(20);
340
    //Set bus speed (according of 8MHz OSC. -> DL = Fosc/(16*Fbauds*DIV)); 
341
    //DIV = 1 or 4 (see TL16C datasheet p.14), we use here DIV = 1 
342
    writePortD(0x00, DLH_REG); //Always 0x00 in our cfg... MAX 12MHz
343
    //_delay_ms(1);
344
    setWait(20);
345
    //writePortA(busSpeed > 2 ? DL_38400_BAUDS : baudsValues[busSpeed], DLL_REG);
346
    writePortD(busSpeed, DLL_REG);
347
    //_delay_ms(1);
348
    setWait(20);
349
    
350
    regVal = readPortD(LCR_REG);
351
    regVal &= ~(DLAB_ERF_EN_BIT); //set LCR[7] = 0 -> disable divisor latch mode
352
    
353
    //regVal |= dataBits > 3 ? TL16C_WORD_8BITS : wordValues[dataBits]; //set 8bits mode
354
    //regVal |= (stopBit > 1 ? TL16C_STOPBIT_TWO : stopBitValues[stopBit]) << 2; //set stop bits
355
    //regVal |= (parity > 2 ? TL16C_PARITY_EVEN : parityValues[parity]) << 3; //set stop bits
356
    regVal |= dataBits; //set 8bits mode
357
    regVal |= stopBit << 2; //set stop bits
358
    regVal |= parity << 3; //set stop bits
359
    writePortD(regVal, LCR_REG);
360
    //_delay_ms(1);
361
    setWait(20);
362
    writePortD(0x01, FCR_REG); //enable FIFO
363
    setWait(20);
364
}
365

    
366

    
367

    
368
//////////////////////////////////////////////
369
//UART send/reiceive
370

    
371
void txWriteA(uint8_t b)
372
{
373
    writePortA(b, THR_REG); //write to Transmit Holding (that goes into TX FIFO buffer)
374
}
375

    
376

    
377
void txWriteB(uint8_t b)
378
{
379
    writePortB(b, THR_REG); //write to Transmit Holding (that goes into TX FIFO buffer)
380
}
381

    
382

    
383
void txWriteC(uint8_t b)
384
{
385
    writePortC(b, THR_REG); //write to Transmit Holding (that goes into TX FIFO buffer)
386
}
387

    
388

    
389
void txWriteD(uint8_t b)
390
{
391
    writePortD(b, THR_REG); //write to Transmit Holding (that goes into TX FIFO buffer)
392
}
393

    
394

    
395

    
396
uint8_t rxReadA(void)
397
{
398
    return readPortA(RHR_REG); //read Receive Holding (from RX FIFO buffer)
399
}
400

    
401

    
402
uint8_t rxReadB(void)
403
{
404
    return readPortB(RHR_REG); //read Receive Holding (from RX FIFO buffer)
405
}
406

    
407

    
408
uint8_t rxReadC(void)
409
{
410
    return readPortC(RHR_REG); //read Receive Holding (from RX FIFO buffer)
411
}
412

    
413

    
414
uint8_t rxReadD(void)
415
{
416
    return readPortD(RHR_REG); //read Receive Holding (from RX FIFO buffer)
417
}
418

    
419

    
420
////////////////////////////////////////
421
//RX buf state functions
422

    
423
bool portA_available()
424
{
425
    return (readPortA(LSR_REG) & 0x01); //check if RX FIFO buffer has at least one byte available
426
}
427

    
428

    
429
bool portB_available()
430
{
431
    return (readPortB(LSR_REG) & 0x01); //check if RX FIFO buffer has at least one byte available
432
}
433

    
434

    
435
bool portC_available()
436
{
437
    return (readPortC(LSR_REG) & 0x01); //check if RX FIFO buffer has at least one byte available
438
}
439

    
440

    
441
bool portD_available()
442
{
443
    return (readPortD(LSR_REG) & 0x01); //check if RX FIFO buffer has at least one byte available
444
}
445

    
446

    
447
///////////////////////////////////////////////////////////////////////
448
//Parity configuration status
449

    
450
//get status if port has been configured with a parity into the frame
451
bool getParitySetA()
452
{
453
    return _portA_parity_set;
454
}
455

    
456
bool getParitySetB()
457
{
458
    return _portB_parity_set;
459
}
460

    
461
bool getParitySetC()
462
{
463
    return _portC_parity_set;
464
}
465

    
466
bool getParitySetD()
467
{
468
    return _portD_parity_set;
469
}
470

    
471

    
472

    
473
//Get parity/stopbit error status when frame received on port
474

    
475
bool getErrorStatusA()
476
{
477
    return ((readPortA(LSR_REG) & 0x80) == 0x80);
478
}
479

    
480
bool getErrorStatusB()
481
{
482
    return ((readPortB(LSR_REG) & 0x80) == 0x80);
483
}
484

    
485
bool getErrorStatusC()
486
{
487
    return ((readPortC(LSR_REG) & 0x80) == 0x80);
488
}
489

    
490
bool getErrorStatusD()
491
{
492
    return ((readPortD(LSR_REG) & 0x80) == 0x80);
493
}
494

    
495

    
496
///////////////////////////////////////////////////////
497
//write functions
498

    
499

    
500

    
501
void writePortA(uint8_t reg, uint8_t addr)
502
{
503
    DATADIR(0xFF); //set I/O on write mode
504
    ADDRWRITE(addr); //search uartn register
505
    DATAWRITE(reg); //write data
506
    CLRCSA; //enable uartA call
507
    setWait(3);
508
    CLRWR; //enable write mode
509
    setWait(3);
510
    SETWR; //disable write mode
511
    setWait(3);
512
    SETCSA; //disable uartA call
513
    DATADIR(0x00); //set input mode (to reduce power consumption)
514
}
515

    
516
void writePortB(uint8_t reg, uint8_t addr)
517
{
518
    DATADIR(0xFF); //set I/O on write mode
519
    ADDRWRITE(addr); //search uartn register
520
    DATAWRITE(reg); //write data
521
    CLRCSB; //enable uartA call
522
    setWait(3);
523
    CLRWR; //enable write mode
524
    setWait(3);
525
    SETWR; //disable write mode
526
    setWait(3);
527
    SETCSB; //disable uartA call
528
    DATADIR(0x00); //set input mode (to reduce power consumption)
529
}
530

    
531
void writePortC(uint8_t reg, uint8_t addr)
532
{
533
    DATADIR(0xFF); //set I/O on write mode
534
    ADDRWRITE(addr); //search uartn register
535
    DATAWRITE(reg); //write data
536
    CLRCSC; //enable uartA call
537
    setWait(3);
538
    CLRWR; //enable write mode
539
    setWait(3);
540
    SETWR; //disable write mode
541
    setWait(3);
542
    SETCSC; //disable uartA call
543
    DATADIR(0x00); //set input mode (to reduce power consumption)
544
}
545

    
546
void writePortD(uint8_t reg, uint8_t addr)
547
{
548
    DATADIR(0xFF); //set I/O on write mode
549
    ADDRWRITE(addr); //search uartn register
550
    DATAWRITE(reg); //write data
551
    CLRCSD; //enable uartA call
552
    setWait(3);
553
    CLRWR; //enable write mode
554
    setWait(3);
555
    SETWR; //disable write mode
556
    setWait(3);
557
    SETCSD; //disable uartA call
558
    DATADIR(0x00); //set input mode (to reduce power consumption)
559
}
560

    
561

    
562
///////////////////////////////////////////////////////
563
//read functions
564

    
565

    
566
uint8_t readPortA(uint8_t addr)
567
{
568
    uint8_t result;
569
    DATADIR(0x00); //set I/O on read mode
570
    ADDRWRITE(addr); //search uartn register
571
    CLRCSA; //enable uartA call
572
    setWait(3);
573
    CLRRD; //enable read mode
574
    setWait(3);
575
    result = PORTD.IN; //set I/O on read mode
576
    setWait(3);
577
    SETRD; //disable read mode
578
    setWait(3);
579
    SETCSA; //hang up uartA call
580
    return result;
581
}
582

    
583
uint8_t readPortB(uint8_t addr)
584
{
585
    uint8_t result;
586
    DATADIR(0x00); //set I/O on read mode
587
    ADDRWRITE(addr); //search uartn register
588
    CLRCSB; //enable uartB call
589
    setWait(3);
590
    CLRRD; //enable read mode
591
    setWait(3);
592
    result = PORTD.IN; //set I/O on read mode
593
    setWait(3);
594
    SETRD; //disable read mode
595
    setWait(3);
596
    SETCSB; //hang up uartB call
597
    return result;
598
}
599

    
600
uint8_t readPortC(uint8_t addr)
601
{
602
    uint8_t result;
603
    DATADIR(0x00); //set I/O on read mode
604
    ADDRWRITE(addr); //search uartn register
605
    CLRCSC; //enable uartC call
606
    setWait(3);
607
    CLRRD; //enable read mode
608
    setWait(3);
609
    result = PORTD.IN; //set I/O on read mode
610
    setWait(3);
611
    SETRD; //disable read mode
612
    setWait(3);
613
    SETCSC; //hang up uartC call
614
    return result;
615
}
616

    
617
uint8_t readPortD(uint8_t addr)
618
{
619
    uint8_t result;
620
    DATADIR(0x00); //set I/O on read mode
621
    ADDRWRITE(addr); //search uartn register
622
    CLRCSD; //enable uartD call
623
    setWait(3);
624
    CLRRD; //enable read mode
625
    setWait(3);
626
    result = PORTD.IN; //set I/O on read mode
627
    setWait(3);
628
    SETRD; //disable read mode
629
    setWait(3);
630
    SETCSD; //hang up uartD call
631
    return result;
632
}
633

    
634

    
635

    
636

    
637

    
638
///////////////////////////////////////////
639
//Miscellaneous functions
640

    
641
void setWait(uint16_t cnt)
642
{
643
    uint16_t k = 0;
644
    while(k < cnt)
645
    {
646
        asm("nop");
647
        k++;
648
    }
649
}
650

    
651

    
652

    
653

    
654

    
655
#endif        /* XC_HEADER_TEMPLATE_H */
656